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Add a equiv test too

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This commit is contained in:
Eddie Hung 2019-11-19 17:05:14 -08:00
parent 90c5ca330c
commit 1cc106452f
2 changed files with 23 additions and 0 deletions
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7
tests/various/abc9.v
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@ -9,3 +9,10 @@ wire w;
unknown u(~i, w);
unknown2 u2(w, o);
endmodule
module abc9_test031(input clk, d, r, output reg q);
initial q = 1'b0;
always @(negedge clk or negedge r)
if (r) q <= 1'b0;
else q <= d;
endmodule