mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-22 20:32:07 +00:00
Code Activity

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

Browse source
This commit is contained in:
Clifford Wolf 2014-07-31 13:19:47 +02:00
parent 1202f7aa4b
commit 1cb25c05b3
41 changed files with 790 additions and 665 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/extract.cc
View file

@ -296,7 +296,7 @@ namespace
SigSet<std::pair<std::string, int>> sig2port;
// create new cell
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
// create cell ports
for (auto &it : needle->wires_) {

2
passes/techmap/techmap.cc
View file

@ -161,7 +161,7 @@ struct TechmapWorker
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
break;
}