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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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1202f7aa4b
commit
1cb25c05b3
41 changed files with 790 additions and 665 deletions
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@ -57,7 +57,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
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static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
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{
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std::stringstream sstr;
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sstr << "$procmux$" << (RTLIL::autoidx++);
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sstr << "$procmux$" << (autoidx++);
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RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
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@ -127,7 +127,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
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log_assert(when_signal.size() == else_signal.size());
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std::stringstream sstr;
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sstr << "$procmux$" << (RTLIL::autoidx++);
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sstr << "$procmux$" << (autoidx++);
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// the trivial cases
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if (compare.size() == 0 || when_signal == else_signal)
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