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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

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This commit is contained in:
Clifford Wolf 2014-07-31 13:19:47 +02:00
parent 1202f7aa4b
commit 1cb25c05b3
41 changed files with 790 additions and 665 deletions
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6
passes/proc/proc_dff.cc
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@ -122,7 +122,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
}
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
@ -144,7 +144,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
{
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
sstr << "$procdff$" << (autoidx++);
RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
@ -191,7 +191,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
{
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff");
cell->attributes = proc->attributes;