Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

passes/abc/abc.cc

@@ -313,7 +313,7 @@ static void handle_loops()
 			}
 
 			std::stringstream sstr;
-			sstr << "$abcloop$" << (RTLIL::autoidx++);
+			sstr << "$abcloop$" << (autoidx++);
 			RTLIL::Wire *wire = module->addWire(sstr.str());
 
 			bool first_line = true;
@@ -400,7 +400,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 		std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff)
 {
 	module = current_module;
-	map_autoidx = RTLIL::autoidx++;
+	map_autoidx = autoidx++;
 
 	signal_map.clear();
 	signal_list.clear();

passes/cmds/design.cc

@@ -22,6 +22,8 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
+YOSYS_NAMESPACE_BEGIN
+
 std::map<std::string, RTLIL::Design*> saved_designs;
 std::vector<RTLIL::Design*> pushed_designs;
 
@@ -249,3 +251,5 @@ struct DesignPass : public Pass {
 	}
 } DesignPass;
 
+YOSYS_NAMESPACE_END
+

passes/fsm/fsm_extract.cc

@@ -270,7 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 
 	// create fsm cell
 
-	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm");
+	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
 	fsm_cell->set("\\CLK", clk);
 	fsm_cell->set("\\ARST", arst);
 	fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
@@ -296,7 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
 		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
-		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
+		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
 	}
 }

passes/memory/memory_collect.cc

@@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	}
 
 	std::stringstream sstr;
-	sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++);
+	sstr << "$mem$" << memory->name << "$" << (autoidx++);
 
 	RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
 	mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);

passes/memory/memory_dff.cc

@@ -113,7 +113,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	sig.sort_and_unify();
 
 	std::stringstream sstr;
-	sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
+	sstr << "$memory_dff_disconnected$" << (autoidx++);
 
 	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 

passes/memory/memory_map.cc

@@ -41,7 +41,7 @@ static std::string genid(std::string name, std::string token1 = "", int i = -1,
 	if (k >= 0)
 		sstr << "[" << k << "]";
 
-	sstr << token4 << "$" << (RTLIL::autoidx++);
+	sstr << token4 << "$" << (autoidx++);
 	return sstr.str();
 }
 

passes/memory/memory_unpack.cc

@@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
 
 	while (module->memories.count(mem_name) != 0)
-		mem_name += stringf("_%d", RTLIL::autoidx++);
+		mem_name += stringf("_%d", autoidx++);
 
 	RTLIL::Memory *mem = new RTLIL::Memory;
 	mem->name = mem_name;

passes/proc/proc_dff.cc

@@ -122,7 +122,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 	}
 
 	std::stringstream sstr;
-	sstr << "$procdff$" << (RTLIL::autoidx++);
+	sstr << "$procdff$" << (autoidx++);
 
 	RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
 	cell->attributes = proc->attributes;
@@ -144,7 +144,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 		bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
 {
 	std::stringstream sstr;
-	sstr << "$procdff$" << (RTLIL::autoidx++);
+	sstr << "$procdff$" << (autoidx++);
 
 	RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
 	RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
@@ -191,7 +191,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
 		bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
 {
 	std::stringstream sstr;
-	sstr << "$procdff$" << (RTLIL::autoidx++);
+	sstr << "$procdff$" << (autoidx++);
 
 	RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff");
 	cell->attributes = proc->attributes;

passes/proc/proc_mux.cc

@@ -57,7 +57,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
 static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
 {
 	std::stringstream sstr;
-	sstr << "$procmux$" << (RTLIL::autoidx++);
+	sstr << "$procmux$" << (autoidx++);
 
 	RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
 
@@ -127,7 +127,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	log_assert(when_signal.size() == else_signal.size());
 
 	std::stringstream sstr;
-	sstr << "$procmux$" << (RTLIL::autoidx++);
+	sstr << "$procmux$" << (autoidx++);
 
 	// the trivial cases
 	if (compare.size() == 0 || when_signal == else_signal)

passes/techmap/extract.cc

@@ -296,7 +296,7 @@ namespace
 		SigSet<std::pair<std::string, int>> sig2port;
 
 		// create new cell
-		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
+		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
 
 		// create cell ports
 		for (auto &it : needle->wires_) {

passes/techmap/techmap.cc

@@ -161,7 +161,7 @@ struct TechmapWorker
 			for (auto &it : tpl->cells_)
 				if (it.first == "\\_TECHMAP_REPLACE_") {
 					orig_cell_name = cell->name;
-					module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
+					module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
 					break;
 				}