Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

frontends/verilog/verilog_frontend.cc

@@ -34,6 +34,7 @@
 #include <sstream>
 #include <stdarg.h>
 
+YOSYS_NAMESPACE_BEGIN
 using namespace VERILOG_FRONTEND;
 
 // use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
@@ -376,3 +377,5 @@ struct VerilogDefaults : public Pass {
 	}
 } VerilogDefaults;
 
+YOSYS_NAMESPACE_END
+