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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

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This commit is contained in:
Clifford Wolf 2014-07-31 13:19:47 +02:00
parent 1202f7aa4b
commit 1cb25c05b3
41 changed files with 790 additions and 665 deletions
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6
frontends/ast/ast.cc
View file

@ -34,6 +34,8 @@
#include <stdarg.h>
#include <math.h>
YOSYS_NAMESPACE_BEGIN
using namespace AST;
using namespace AST_INTERNAL;
@ -806,7 +808,7 @@ RTLIL::Const AstNode::realAsConst(int width)
{
double v = round(realvalue);
RTLIL::Const result;
if (!isfinite(v)) {
if (!std::isfinite(v)) {
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
} else {
bool is_negative = v < 0;
@ -1087,3 +1089,5 @@ void AST::use_internal_line_num()
get_line_num = &internal_get_line_num;
}
YOSYS_NAMESPACE_END

4
frontends/ast/ast.h
View file

@ -33,6 +33,8 @@
#include <stdint.h>
#include <set>
YOSYS_NAMESPACE_BEGIN
namespace AST
{
// all node types, type2str() must be extended
@ -285,4 +287,6 @@ namespace AST_INTERNAL
struct ProcessGenerator;
}
YOSYS_NAMESPACE_END
#endif

24
frontends/ast/genrtlil.cc
View file

@ -34,6 +34,8 @@
#include <stdarg.h>
#include <algorithm>
YOSYS_NAMESPACE_BEGIN
using namespace AST;
using namespace AST_INTERNAL;
@ -41,7 +43,7 @@ using namespace AST_INTERNAL;
static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@ -75,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
}
std::stringstream sstr;
sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@ -104,7 +106,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@ -139,7 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
log_assert(cond.size() == 1);
std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@ -201,7 +203,7 @@ struct AST_INTERNAL::ProcessGenerator
// generate process and simple root case
proc = new RTLIL::Process;
proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, RTLIL::autoidx++);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n",
@ -294,7 +296,7 @@ struct AST_INTERNAL::ProcessGenerator
wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
if (chunk.wire->name.find('$') != std::string::npos)
wire_name += stringf("$%d", RTLIL::autoidx++);
wire_name += stringf("$%d", autoidx++);
} while (current_module->wires_.count(wire_name) > 0);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
@ -1189,7 +1191,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMRD:
{
std::stringstream sstr;
sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -1220,7 +1222,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMWR:
{
std::stringstream sstr;
sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -1241,7 +1243,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1);
cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
}
break;
@ -1257,7 +1259,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(en.size() == 1);
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -1399,3 +1401,5 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RT
return sig;
}
YOSYS_NAMESPACE_END

60
frontends/ast/simplify.cc
View file

@ -34,6 +34,8 @@
#include <stdarg.h>
#include <math.h>
YOSYS_NAMESPACE_BEGIN
using namespace AST;
using namespace AST_INTERNAL;
@ -624,7 +626,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
id2ast->meminfo(mem_width, mem_size, addr_bits);
std::stringstream sstr;
sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string wire_id = sstr.str();
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
@ -744,7 +746,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
buf = new AstNode(AST_GENBLOCK, body_ast->clone());
if (buf->str.empty()) {
std::stringstream sstr;
sstr << "$genblock$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$genblock$" << filename << ":" << linenum << "$" << (autoidx++);
buf->str = sstr.str();
}
std::map<std::string, std::string> name_map;
@ -1091,7 +1093,7 @@ skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && type == AST_ASSERT && current_block != NULL)
{
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
AstNode *wire_check = new AstNode(AST_WIRE);
@ -1166,7 +1168,7 @@ skip_dynamic_range_lvalue_expansion:;
(children[0]->children.size() == 1 || children[0]->children.size() == 2))
{
std::stringstream sstr;
sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
if (type == AST_ASSIGN_EQ)
@ -1364,27 +1366,27 @@ skip_dynamic_range_lvalue_expansion:;
}
newNode = new AstNode(AST_REALVALUE);
if (str == "\\$ln") newNode->realvalue = log(x);
else if (str == "\\$log10") newNode->realvalue = log10(x);
else if (str == "\\$exp") newNode->realvalue = exp(x);
else if (str == "\\$sqrt") newNode->realvalue = sqrt(x);
else if (str == "\\$pow") newNode->realvalue = pow(x, y);
else if (str == "\\$floor") newNode->realvalue = floor(x);
else if (str == "\\$ceil") newNode->realvalue = ceil(x);
else if (str == "\\$sin") newNode->realvalue = sin(x);
else if (str == "\\$cos") newNode->realvalue = cos(x);
else if (str == "\\$tan") newNode->realvalue = tan(x);
else if (str == "\\$asin") newNode->realvalue = asin(x);
else if (str == "\\$acos") newNode->realvalue = acos(x);
else if (str == "\\$atan") newNode->realvalue = atan(x);
else if (str == "\\$atan2") newNode->realvalue = atan2(x, y);
else if (str == "\\$hypot") newNode->realvalue = hypot(x, y);
else if (str == "\\$sinh") newNode->realvalue = sinh(x);
else if (str == "\\$cosh") newNode->realvalue = cosh(x);
else if (str == "\\$tanh") newNode->realvalue = tanh(x);
else if (str == "\\$asinh") newNode->realvalue = asinh(x);
else if (str == "\\$acosh") newNode->realvalue = acosh(x);
else if (str == "\\$atanh") newNode->realvalue = atanh(x);
if (str == "\\$ln") newNode->realvalue = ::log(x);
else if (str == "\\$log10") newNode->realvalue = ::log10(x);
else if (str == "\\$exp") newNode->realvalue = ::exp(x);
else if (str == "\\$sqrt") newNode->realvalue = ::sqrt(x);
else if (str == "\\$pow") newNode->realvalue = ::pow(x, y);
else if (str == "\\$floor") newNode->realvalue = ::floor(x);
else if (str == "\\$ceil") newNode->realvalue = ::ceil(x);
else if (str == "\\$sin") newNode->realvalue = ::sin(x);
else if (str == "\\$cos") newNode->realvalue = ::cos(x);
else if (str == "\\$tan") newNode->realvalue = ::tan(x);
else if (str == "\\$asin") newNode->realvalue = ::asin(x);
else if (str == "\\$acos") newNode->realvalue = ::acos(x);
else if (str == "\\$atan") newNode->realvalue = ::atan(x);
else if (str == "\\$atan2") newNode->realvalue = ::atan2(x, y);
else if (str == "\\$hypot") newNode->realvalue = ::hypot(x, y);
else if (str == "\\$sinh") newNode->realvalue = ::sinh(x);
else if (str == "\\$cosh") newNode->realvalue = ::cosh(x);
else if (str == "\\$tanh") newNode->realvalue = ::tanh(x);
else if (str == "\\$asinh") newNode->realvalue = ::asinh(x);
else if (str == "\\$acosh") newNode->realvalue = ::acosh(x);
else if (str == "\\$atanh") newNode->realvalue = ::atanh(x);
else log_abort();
goto apply_newNode;
}
@ -1423,7 +1425,7 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *decl = current_scope[str];
std::stringstream sstr;
sstr << "$func$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++) << "$";
sstr << "$func$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++) << "$";
std::string prefix = sstr.str();
size_t arg_count = 0;
@ -1988,7 +1990,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
mem2reg_set.count(children[0]->id2ast) > 0 && children[0]->children[0]->children[0]->type != AST_CONSTANT)
{
std::stringstream sstr;
sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
@ -2059,7 +2061,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
else
{
std::stringstream sstr;
sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
@ -2421,3 +2423,5 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
return AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed);
}
YOSYS_NAMESPACE_END