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Renaming BRAM memory tests for the sake of uniformity

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This commit is contained in:
Diego H 2019-12-13 09:33:18 -06:00
parent 751a18d7e9
commit 1c96345587
2 changed files with 6 additions and 6 deletions
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0
tests/arch/common/memory_params.v → tests/arch/common/blockram_params.v
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12
tests/arch/xilinx/memory_params.ys → tests/arch/xilinx/blockram_params.ys
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@ -1,28 +1,28 @@
## TODO: Not running equivalence checking because BRAM models does not exists ## TODO: Not running equivalence checking because BRAM models does not exists
## currently. Checking instance counts instead. ## currently. Checking instance counts instead.
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RAMB18E1
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RAMB18E1
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RAMB18E1
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
@ -30,7 +30,7 @@ select -assert-count 1 t:RAMB18E1
# Anything memory bits < 1024 -> LUTRAM # Anything memory bits < 1024 -> LUTRAM
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
@ -39,7 +39,7 @@ select -assert-count 4 t:RAM128X1D
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/blockram_params.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp