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abc9_ops: implement a requireds_cache

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This commit is contained in:
Eddie Hung 2020-01-14 15:20:04 -08:00
parent 0e4285ca0d
commit 1c88a6c240
1 changed files with 34 additions and 26 deletions
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60
passes/techmap/abc9_ops.cc
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@ -387,7 +387,7 @@ void prep_delays(RTLIL::Design *design)
std::set<int> delays; std::set<int> delays;
pool<Module*> flops; pool<Module*> flops;
std::vector<Cell*> cells; std::vector<Cell*> cells;
std::map<int,std::vector<int>> requireds; dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
if (module->processes.size() > 0) { if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(module)); log("Skipping module %s as it contains processes.\n", log_id(module));
@ -418,48 +418,56 @@ void prep_delays(RTLIL::Design *design)
} }
delays.clear(); delays.clear();
requireds.clear();
for (auto cell : cells) { for (auto cell : cells) {
RTLIL::Module* inst_module = module->design->module(cell->type); RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module); log_assert(inst_module);
auto &cell_requireds = requireds_cache[cell->type];
for (auto &conn : cell->connections_) { for (auto &conn : cell->connections_) {
auto port_wire = inst_module->wire(conn.first); auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_input) if (!port_wire->port_input)
continue; continue;
auto it = port_wire->attributes.find("\\abc9_required"); auto r = cell_requireds.insert(conn.first);
if (it == port_wire->attributes.end()) auto &requireds = r.first->second;
continue; if (r.second) {
auto it = port_wire->attributes.find("\\abc9_required");
int count = 0; if (it == port_wire->attributes.end())
requireds.clear(); continue;
if (it->second.flags == 0) { if (it->second.flags == 0) {
count = 1; int delay = it->second.as_int();
requireds[it->second.as_int()].push_back(0); delays.insert(delay);
requireds.emplace_back(delay);
}
else
for (const auto &tok : split_tokens(it->second.decode_string())) {
int delay = atoi(tok.c_str());
delays.insert(delay);
requireds.push_back(delay);
}
} }
else
for (const auto &tok : split_tokens(it->second.decode_string())) if (requireds.empty())
requireds[atoi(tok.c_str())].push_back(count++); continue;
if (count > 1 && count != GetSize(port_wire)) if (GetSize(requireds) > 1 && GetSize(requireds) != GetSize(port_wire))
log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
GetSize(port_wire), log_signal(it->second), count); GetSize(port_wire), log_signal(port_wire->attributes.at("\\abc9_required")), GetSize(requireds));
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
for (const auto &i : requireds) { auto it = requireds.begin();
for (int i = 0; i < GetSize(conn.second); ++i) {
#ifndef NDEBUG #ifndef NDEBUG
if (ys_debug(1)) { if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen; static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first); if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
} }
#endif #endif
delays.insert(i.first); auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
for (auto offset : i.second) { box->setPort(ID(I), conn.second[i]);
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); box->setPort(ID(O), O[i]);
box->setPort(ID(I), conn.second[offset]); box->setParam(ID(DELAY), *it);
box->setPort(ID(O), O[offset]); if (requireds.size() > 1)
box->setParam(ID(DELAY), i.first); it++;
conn.second[offset] = O[offset]; conn.second[i] = O[i];
}
} }
} }
} }