mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 10:50:25 +00:00
Code Activity

Reject if not minlen from inside pattern matcher

Browse source
This commit is contained in:
Eddie Hung 2019-08-21 14:26:24 -07:00
parent cab2bd083e
commit 1c7d721558
2 changed files with 11 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

16
passes/pmgen/xilinx_srl.cc
View file

@ -30,14 +30,11 @@ bool did_something;
#include "passes/pmgen/ice40_dsp_pm.h"
#include "passes/pmgen/peepopt_pm.h"
void reduce_chain(xilinx_srl_pm &pm, int minlen)
void reduce_chain(xilinx_srl_pm &pm)
{
auto &st = pm.st_reduce;
auto &ud = pm.ud_reduce;
if (GetSize(ud.longest_chain) < minlen)
return;
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
auto last_cell = ud.longest_chain.back();
@ -115,9 +112,14 @@ struct XilinxSrlPass : public Pass {
}
extra_args(args, argidx, design);
auto f = std::bind(reduce_chain, std::placeholders::_1, minlen);
for (auto module : design->selected_modules())
while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {}
for (auto module : design->selected_modules()) {
bool did_something = false;
do {
auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_reduce.minlen = minlen;
did_something = pm.run_reduce(reduce_chain);
} while (did_something);
}
}
} XilinxSrlPass;