mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 12:07:51 +00:00
Code Activity

Merge branch 'xaig' into xc7mux

Browse source
This commit is contained in:
Eddie Hung 2019-06-27 11:55:11 -07:00
commit 1c79a32276
4 changed files with 38 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

3
CHANGELOG
View file

@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- Added "pmux2shiftx -norange"
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
@ -52,7 +53,7 @@ Yosys 0.7 .. Yosys 0.8
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- Added support for systemVerilog "++" and "--" operators
- Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive