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Update abc_* attr in ecp5 and ice40

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This commit is contained in:
Eddie Hung 2019-08-16 15:56:57 -07:00
parent 4fe307f1bc
commit 1c57b1e7ea
2 changed files with 21 additions and 11 deletions
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20
techlibs/ecp5/cells_sim.v
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@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
endmodule endmodule
// --------------------------------------- // ---------------------------------------
(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) (* abc_box_id=1, lib_whitebox *)
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, module CCU2C(
output S0, S1, COUT); (* abc_carry_in *) input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry_out *) output COUT
);
parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000; parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES"; parameter INJECT1_0 = "YES";
@ -104,11 +107,12 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule endmodule
// --------------------------------------- // ---------------------------------------
//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) //(* abc_box_id=2 *)
module TRELLIS_DPR16X4 ( module TRELLIS_DPR16X4 (
input [3:0] DI, (* abc_scc_break *) input [3:0] DI,
input [3:0] WAD, (* abc_scc_break *) input [3:0] WAD,
input WRE, WCK, (* abc_scc_break *) input WRE,
input WCK,
input [3:0] RAD, input [3:0] RAD,
output [3:0] DO output [3:0] DO
); );

10
techlibs/ice40/cells_sim.v
View file

@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI); assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) (* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); module \$__ICE40_FULL_ADDER (
(* abc_carry_out *) output CO,
output O,
input A,
input B,
(* abc_carry_in *) input CI
);
SB_CARRY carry ( SB_CARRY carry (
.I0(A), .I0(A),
.I1(B), .I1(B),