mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 07:27:58 +00:00
Code Activity

Update abc_* attr in ecp5 and ice40

Browse source
This commit is contained in:
Eddie Hung 2019-08-16 15:56:57 -07:00
parent 4fe307f1bc
commit 1c57b1e7ea
2 changed files with 21 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

10
techlibs/ice40/cells_sim.v
View file

@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry_out *) output CO,
output O,
input A,
input B,
(* abc_carry_in *) input CI
);
SB_CARRY carry (
.I0(A),
.I1(B),