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https://github.com/YosysHQ/yosys
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Added "write_smt2 -bv" and other write_smt2 improvements
This commit is contained in:
Clifford Wolf
parent
b6a7e21d2e
commit
1c3d51375f
1 changed files with 149 additions and 168 deletions
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@ -32,184 +32,155 @@ struct Smt2Worker
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CellTypes ct;
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SigMap sigmap;
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RTLIL::Module *module;
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bool bvmode;
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int idcounter;
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std::vector<std::string> decls, clauses, trans;
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std::map<RTLIL::SigBit, std::string> bool_cache;
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std::map<RTLIL::IdString, std::vector<RTLIL::Cell*>> cells_by_type;
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std::vector<std::string> decls, trans;
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std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
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std::set<RTLIL::Cell*> exported_cells;
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Smt2Worker(RTLIL::Module *module) : ct(module->design), sigmap(module), module(module)
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std::map<RTLIL::SigBit, std::pair<int, int>> fcache;
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std::map<int, int> bvsizes;
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Smt2Worker(RTLIL::Module *module, bool bvmode) : ct(module->design), sigmap(module), module(module), bvmode(bvmode), idcounter(0)
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{
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decls.push_back(stringf("(declare-sort |%s_s| 0)\n", log_id(module)));
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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bool is_input = ct.cell_input(cell->type, conn.first);
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bool is_output = ct.cell_output(cell->type, conn.first);
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if (is_output && !is_input)
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for (auto bit : sigmap(conn.second)) {
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if (bit_driver.count(bit))
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log_error("Found multiple drivers for %s.\n", log_signal(bit));
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bit_driver[bit] = cell;
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}
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else if (is_output || !is_input)
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log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
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log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
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}
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}
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void register_bool(RTLIL::SigBit bit, int id)
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{
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sigmap.apply(bit);
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log_assert(fcache.count(bit) == 0);
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fcache[bit] = std::pair<int, int>(id, -1);
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}
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std::string get_bool(RTLIL::SigBit bit, const char *state_name = "state")
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{
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sigmap.apply(bit);
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if (bit.wire == nullptr)
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return bit.data == RTLIL::State::S1 ? "true" : "false";
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if (bit_driver.count(bit))
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export_cell(bit_driver.at(bit));
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if (!bool_cache.count(bit)) {
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std::string name = stringf("|%s_n %s %d|", log_id(module), log_id(bit.wire), bit.offset);
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for (auto &c : name)
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if (c == '\\') c = '/';
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decls.push_back(stringf("(declare-fun %s (|%s_s|) Bool)\n", name.c_str(), log_id(module)));
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bool_cache[bit] = name;
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if (fcache.count(bit) == 0) {
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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log_id(module), idcounter, log_id(module), log_signal(bit)));
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register_bool(bit, idcounter++);
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}
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return stringf("(%s %s)", bool_cache.at(bit).c_str(), state_name);
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auto f = fcache.at(bit);
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log_assert(f.second == -1);
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return stringf("(|%s#%d| %s)", log_id(module), f.first, state_name);
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}
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void make_wire(RTLIL::Wire *wire)
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std::string get_bv(RTLIL::SigSpec sig, const char *state_name = "state")
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{
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for (int i = 0; i < GetSize(wire); i++)
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get_bool(RTLIL::SigBit(wire, i));
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std::vector<std::string> subexpr;
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for (auto bit : sig)
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subexpr.push_back(stringf("(ite %s #b1 #b0)", get_bool(bit, state_name).c_str()));
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if (GetSize(subexpr) > 1) {
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std::string expr = "(concat";
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for (int i = GetSize(subexpr)-1; i >= 0; i--)
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expr += " " + subexpr[i];
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return expr + ")";
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} else {
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log_assert(GetSize(subexpr) == 1);
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return subexpr[0];
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}
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}
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void run_gates()
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void export_gate(RTLIL::Cell *cell, std::string expr)
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{
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// basic gate-level logic cell types
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RTLIL::SigBit bit = sigmap(cell->getPort("\\Y")[0]);
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std::string processed_expr;
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for (auto cell : cells_by_type["$_BUF_"])
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clauses.push_back(stringf(" (= %s %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_BUF_");
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for (char ch : expr) {
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if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A")[0]);
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else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B")[0]);
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else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C")[0]);
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else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D")[0]);
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else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S")[0]);
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else processed_expr += ch;
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}
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for (auto cell : cells_by_type["$_NOT_"])
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clauses.push_back(stringf(" (distinct %s %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_NOT_");
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
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log_id(module), idcounter, log_id(module), processed_expr.c_str(), log_signal(bit)));
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register_bool(bit, idcounter++);
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return;
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}
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for (auto cell : cells_by_type["$_AND_"])
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clauses.push_back(stringf(" (= (and %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_AND_");
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void export_cell(RTLIL::Cell *cell)
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{
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if (exported_cells.count(cell))
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return;
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exported_cells.insert(cell);
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for (auto cell : cells_by_type["$_OR_"])
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clauses.push_back(stringf(" (= (or %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_OR_");
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if (cell->type == "$_DFF_P_" || cell->type == "$_DFF_N_")
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{
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std::string expr_d = get_bool(cell->getPort("\\D")[0]);
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std::string expr_q = get_bool(cell->getPort("\\Q")[0], "next_state");
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trans.push_back(stringf(" (= %s %s)\n", expr_d.c_str(), expr_q.c_str()));
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return;
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}
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for (auto cell : cells_by_type["$_XOR_"])
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clauses.push_back(stringf(" (= (xor %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_XOR_");
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if (cell->type == "$_BUF_") return export_gate(cell, "A");
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if (cell->type == "$_NOT_") return export_gate(cell, "(not A)");
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if (cell->type == "$_AND_") return export_gate(cell, "(and A B)");
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if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))");
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if (cell->type == "$_OR_") return export_gate(cell, "(or A B)");
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if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))");
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if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)");
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if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))");
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if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)");
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if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))");
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if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))");
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if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))");
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if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))");
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for (auto cell : cells_by_type["$_MUX_"])
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clauses.push_back(stringf(" (= (ite %s %s %s) %s)\n",
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get_bool(cell->getPort("\\S").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_MUX_");
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// inverted gate-level logic cell types
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for (auto cell : cells_by_type["$_NAND_"])
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clauses.push_back(stringf(" (distinct (and %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_NAND_");
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for (auto cell : cells_by_type["$_NOR_"])
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clauses.push_back(stringf(" (distinct (or %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_NOR_");
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for (auto cell : cells_by_type["$_XNOR_"])
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clauses.push_back(stringf(" (distinct (xor %s %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_XNOR_");
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// advanced cmos-style logic cell types
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for (auto cell : cells_by_type["$_AOI3_"])
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clauses.push_back(stringf(" (distinct (or (and %s %s) %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\C").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_AOI3_");
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for (auto cell : cells_by_type["$_AOI4_"])
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clauses.push_back(stringf(" (distinct (or (and %s %s) (and %s %s)) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\C").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\D").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_AOI4_");
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for (auto cell : cells_by_type["$_OAI3_"])
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clauses.push_back(stringf(" (distinct (or (and %s %s) %s) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\C").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_OAI3_");
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for (auto cell : cells_by_type["$_OAI4_"])
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clauses.push_back(stringf(" (distinct (or (and %s %s) (and %s %s)) %s)\n",
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get_bool(cell->getPort("\\A").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\B").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\C").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\D").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Y").to_single_sigbit()).c_str()));
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cells_by_type.erase("$_OAI4_");
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// simple DFF cells (ignoring clock domains)
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for (auto cell : cells_by_type["$_DFF_P_"])
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trans.push_back(stringf(" (= %s %s)\n",
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get_bool(cell->getPort("\\D").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Q").to_single_sigbit(), "next_state").c_str()));
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cells_by_type.erase("$_DFF_P_");
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for (auto cell : cells_by_type["$_DFF_N_"])
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trans.push_back(stringf(" (= %s %s)\n",
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get_bool(cell->getPort("\\D").to_single_sigbit()).c_str(),
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get_bool(cell->getPort("\\Q").to_single_sigbit(), "next_state").c_str()));
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cells_by_type.erase("$_DFF_N_");
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log_error("Unsupported cell type %s for cell %s.%s.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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void run()
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{
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for (auto port : module->ports)
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make_wire(module->wire(port));
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for (auto cell : module->cells())
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cells_by_type[cell->type].push_back(cell);
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run_gates();
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for (auto &it : cells_by_type)
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log_error("Found %d cells of unsupported type %s in module %s.\n", GetSize(it.second), log_id(it.first), log_id(module));
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for (auto wire : module->wires())
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if (wire->port_id || wire->get_bool_attribute("\\keep")) {
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RTLIL::SigSpec sig = sigmap(wire);
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if (bvmode && GetSize(sig) > 1) {
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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log_id(module), log_id(wire), log_id(module), GetSize(sig), get_bv(sig).c_str()));
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} else {
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for (int i = 0; i < GetSize(sig); i++)
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if (GetSize(sig) > 1)
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decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
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log_id(module), log_id(wire), i, log_id(module), get_bool(sig[i]).c_str()));
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else
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
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log_id(module), log_id(wire), log_id(module), get_bool(sig[i]).c_str()));
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}
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}
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}
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void write(std::ostream &f)
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{
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for (auto it : decls)
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f << it;
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f << stringf("(define-fun |%s_c| ((state |%s_s|)) Bool (and\n", log_id(module), log_id(module));
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for (auto it : clauses)
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f << it;
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f << "true true))\n";
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f << stringf("(define-fun |%s_t| ((state |%s_s|)(next_state |%s_s|)) Bool (and\n", log_id(module), log_id(module), log_id(module));
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for (auto it : trans)
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f << it;
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@ -225,24 +196,32 @@ struct Smt2Backend : public Backend {
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log("\n");
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log(" write_smt2 [options] [filename]\n");
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log("\n");
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log("Write a SMT-LIBv2 description of the current design. For a module with name\n");
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log("'<mod>' this will declare the sort '<mod>_s' and the two functions '<mod>_c'\n");
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log("(of arity 1) and '<mod>_t' (of arity 2).\n");
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log("Write a SMT-LIBv2 [1] description of the current design. For a module with name\n");
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log("'<mod>' this will declare the sort '<mod>_s' (state of the module) and the the\n");
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log("function '<mod>_t' (state transition function).\n");
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log("\n");
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log("The sort represents the state of the module. Additional '<mod>_n' functions are\n");
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log("declared that can be used to access the values of all signals in the module.\n");
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log("The '<mod>_s' sort represents the a module state. Additional '<mod>_n' functions\n");
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log("are provided that can be used to access the values of all signals in the module.\n");
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log("Only ports, and signals with the 'keep' attribute set are made available via\n");
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log("such functions. Without the -bv option, multi-bit wires are exported as\n");
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log("separate functions of type Bool for the individual bits. With the -bv option\n");
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log("multi-bit wires are exported as single functions of type BitVec.\n");
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log("\n");
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log("The '<mod>_c' function evaluates to 'true' when the given state is consistent\n");
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log("with the description of the models.\n");
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log("The '<mod>_t' function evaluates to 'true' when the given pair of states\n");
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log("describes a valid state transition.\n");
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log("\n");
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log("The '<mod>_t' function evaluates to 'true' when the given pair of states is\n");
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log("describes a valid state transition, provided that '<mod>_c' is true for both\n");
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log("states.\n");
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log(" -bv\n");
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log(" enable support for BitVec (FixedSizeBitVectors theory). with this\n");
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log(" option set multi-bit wires are represented using the BitVec sort and\n");
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log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
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log("\n");
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log(" -tpl <template_file>\n");
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log(" use the given template file. the line containing only the token '%%%%'\n");
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log(" is replaced with the regular output of this command.\n");
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log("\n");
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log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n");
|
||||
log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n");
|
||||
log("\n");
|
||||
log("---------------------------------------------------------------------------\n");
|
||||
log("\n");
|
||||
log("Example:\n");
|
||||
|
|
@ -257,8 +236,8 @@ struct Smt2Backend : public Backend {
|
|||
log("\n");
|
||||
log("For this proof we create the following template (test.tpl).\n");
|
||||
log("\n");
|
||||
log(" ; we only need QF_UF for this poof\n");
|
||||
log(" (set-logic QF_UF)\n");
|
||||
log(" ; we need QF_UFBV for this poof\n");
|
||||
log(" (set-logic QF_UFBV)\n");
|
||||
log("\n");
|
||||
log(" ; insert the auto-generated code here\n");
|
||||
log(" %%%%\n");
|
||||
|
|
@ -267,27 +246,23 @@ struct Smt2Backend : public Backend {
|
|||
log(" (declare-fun s1 () test_s)\n");
|
||||
log(" (declare-fun s2 () test_s)\n");
|
||||
log("\n");
|
||||
log(" ; both states are valid and s2 follows s1\n");
|
||||
log(" (assert (test_c s1))\n");
|
||||
log(" (assert (test_c s2))\n");
|
||||
log(" ; state s2 is the successor of state s1\n");
|
||||
log(" (assert (test_t s1 s2))\n");
|
||||
log("\n");
|
||||
log(" ; we are looking for a solution with y non-zero in s1\n");
|
||||
log(" (assert (or (|test_n y 0| s1) (|test_n y 1| s1)\n");
|
||||
log(" (|test_n y 2| s1) (|test_n y 3| s1)))\n");
|
||||
log(" ; we are looking for a model with y non-zero in s1\n");
|
||||
log(" (assert (distinct (|test_n y| s1) #b0000))\n");
|
||||
log("\n");
|
||||
log(" ; we are looking for a solution with y zero in s2\n");
|
||||
log(" (assert (not (or (|test_n y 0| s2) (|test_n y 1| s2)\n");
|
||||
log(" (|test_n y 2| s2) (|test_n y 3| s2))))\n");
|
||||
log(" ; we are looking for a model with y zero in s2\n");
|
||||
log(" (assert (= (|test_n y| s2) #b0000))\n");
|
||||
log("\n");
|
||||
log(" ; is there such a solution?\n");
|
||||
log(" ; is there such a model?\n");
|
||||
log(" (check-sat)\n");
|
||||
log("\n");
|
||||
log("The following yosys script will create a 'test.smt2' file for our proof:\n");
|
||||
log("\n");
|
||||
log(" read_verilog test.v\n");
|
||||
log(" hierarchy; proc; techmap; opt -fast\n");
|
||||
log(" write_smt2 -template test.tpl test.smt2\n");
|
||||
log(" write_smt2 -bv -tpl test.tpl test.smt2\n");
|
||||
log("\n");
|
||||
log("Running 'cvc4 test.smt2' will print 'unsat' because y can never transition\n");
|
||||
log("from non-zero to zero in the test design.\n");
|
||||
|
|
@ -296,17 +271,23 @@ struct Smt2Backend : public Backend {
|
|||
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
std::ifstream template_f;
|
||||
bool bvmode = false;
|
||||
|
||||
log_header("Executing SMT2 backend.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-template" && argidx+1 < args.size()) {
|
||||
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
|
||||
template_f.open(args[++argidx]);
|
||||
if (template_f.fail())
|
||||
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-bv") {
|
||||
bvmode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
|
@ -332,7 +313,7 @@ struct Smt2Backend : public Backend {
|
|||
|
||||
log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
|
||||
|
||||
Smt2Worker worker(module);
|
||||
Smt2Worker worker(module, bvmode);
|
||||
worker.run();
|
||||
worker.write(*f);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue