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Merge pull request #23 from alaindargelas/fix_runtime_write_verilog

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Akash Levy 2024-11-16 17:06:04 -08:00 • committed by GitHub
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backends/verilog/verilog_backend.cc
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@ -2359,7 +2359,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (auto wire : module->wires()) {
wires[wire->port_id] = wire;
}
for (int port_id = 1; port_id < max_port_id; port_id++) {
for (int port_id = 1; port_id <= max_port_id; port_id++) {
Wire *wire = wires[port_id];
if (wire) {
if (port_id != 1)