diff --git a/tests/csa_tree/abc_bench_add8.v b/tests/csa_tree/abc_bench_add8.v
deleted file mode 100644
index 7e61007c5..000000000
--- a/tests/csa_tree/abc_bench_add8.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module abc_bench_add8(
-	input  [7:0] a, b, c, d, e, f, g, h,
-	output [7:0] y
-);
-	assign y = a + b + c + d + e + f + g + h;
-endmodule
diff --git a/tests/csa_tree/add_1bit.v b/tests/csa_tree/add_1bit.v
deleted file mode 100644
index e4b93e8c0..000000000
--- a/tests/csa_tree/add_1bit.v
+++ /dev/null
@@ -1,9 +0,0 @@
-// Edge case for carry shifting
-
-module add_1bit(
-	input  a, b, c,
-	output [1:0] y
-);
-	assign y = a + b + c;
-endmodule
-
diff --git a/tests/csa_tree/add_1bit_wide_out.v b/tests/csa_tree/add_1bit_wide_out.v
deleted file mode 100644
index e1a6ceb51..000000000
--- a/tests/csa_tree/add_1bit_wide_out.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module add_1bit_wide_out(
-	input  a, b, c, d,
-	output [3:0] y
-);
-	assign y = a + b + c + d;
-endmodule
diff --git a/tests/csa_tree/add_chain_16.v b/tests/csa_tree/add_chain_16.v
deleted file mode 100644
index 0a1f12f8c..000000000
--- a/tests/csa_tree/add_chain_16.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module add_chain_16(
-	input  [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
-	input  [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
-	output [15:0] y
-);
-	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
-endmodule
diff --git a/tests/csa_tree/add_chain_2_neg.v b/tests/csa_tree/add_chain_2_neg.v
deleted file mode 100644
index 0e2896c78..000000000
--- a/tests/csa_tree/add_chain_2_neg.v
+++ /dev/null
@@ -1,8 +0,0 @@
-// Shouldnt generate csa tree
-
-module add_chain_2(
-	input  [7:0] a, b,
-	output [7:0] y
-);
-	assign y = a + b;
-endmodule
diff --git a/tests/csa_tree/add_chain_3.v b/tests/csa_tree/add_chain_3.v
deleted file mode 100644
index eea529ead..000000000
--- a/tests/csa_tree/add_chain_3.v
+++ /dev/null
@@ -1,9 +0,0 @@
-// Min chain len
-
-module add_chain_3(
-	input  [7:0] a, b, c,
-	output [7:0] y
-);
-	assign y = a + b + c;
-endmodule
-
diff --git a/tests/csa_tree/add_chain_5.v b/tests/csa_tree/add_chain_5.v
deleted file mode 100644
index 25fb30e1d..000000000
--- a/tests/csa_tree/add_chain_5.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module add_chain_5(
-	input  [11:0] a, b, c, d, e,
-	output [11:0] y
-);
-	assign y = a + b + c + d + e;
-endmodule
-
diff --git a/tests/csa_tree/add_chain_8.v b/tests/csa_tree/add_chain_8.v
deleted file mode 100644
index 96adbc37e..000000000
--- a/tests/csa_tree/add_chain_8.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module add_chain_8(
-	input  [15:0] a, b, c, d, e, f, g, h,
-	output [15:0] y
-);
-	assign y = a + b + c + d + e + f + g + h;
-endmodule
-
diff --git a/tests/csa_tree/add_mixed_widths.v b/tests/csa_tree/add_mixed_widths.v
deleted file mode 100644
index 51836872a..000000000
--- a/tests/csa_tree/add_mixed_widths.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module add_mixed_widths(
-	input  [7:0]  a,
-	input  [3:0]  b,
-	input  [15:0] c,
-	input  [7:0]  d,
-	output [15:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-
diff --git a/tests/csa_tree/add_multi_const.v b/tests/csa_tree/add_multi_const.v
deleted file mode 100644
index 7da78f9de..000000000
--- a/tests/csa_tree/add_multi_const.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module add_multi_const(
-	input  [7:0] x,
-	output [7:0] y
-);
-	assign y = 8'd1 + 8'd2 + 8'd3 + x;
-endmodule
diff --git a/tests/csa_tree/add_multi_fanout.v b/tests/csa_tree/add_multi_fanout.v
deleted file mode 100644
index 4cc7ecab3..000000000
--- a/tests/csa_tree/add_multi_fanout.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module add_multi_fanout(
-	input  [7:0] a, b, c,
-	output [7:0] mid,
-	output [7:0] y
-);
-	wire [7:0] ab = a + b;
-	assign mid = ab;
-	assign y   = ab + c;
-endmodule
-
diff --git a/tests/csa_tree/add_partial_chain.v b/tests/csa_tree/add_partial_chain.v
deleted file mode 100644
index a4f20cfa4..000000000
--- a/tests/csa_tree/add_partial_chain.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module add_partial_chain(
-	input  [7:0] a, b, c, d, e,
-	output [7:0] mid,
-	output [7:0] y
-);
-	wire [7:0] ab = a + b;
-	assign mid = ab;
-	assign y = ab + c + d + e;
-endmodule
diff --git a/tests/csa_tree/add_repeated.v b/tests/csa_tree/add_repeated.v
deleted file mode 100644
index e3337097b..000000000
--- a/tests/csa_tree/add_repeated.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module add_repeated(
-	input  [7:0] a,
-	output [7:0] y
-);
-	assign y = a + a + a + a;
-endmodule
diff --git a/tests/csa_tree/add_signed.v b/tests/csa_tree/add_signed.v
deleted file mode 100644
index 42b9ca7fd..000000000
--- a/tests/csa_tree/add_signed.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module add_signed(
-	input  signed [7:0] a, b, c, d,
-	output signed [9:0] y
-);
-	assign y = a + b + c + d;
-endmodule
diff --git a/tests/csa_tree/add_two_chains.v b/tests/csa_tree/add_two_chains.v
deleted file mode 100644
index d79d9f3d6..000000000
--- a/tests/csa_tree/add_two_chains.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module add_two_chains(
-	input  [7:0] a, b, c, d,
-	input  [7:0] e, f, g, h,
-	output [7:0] y1,
-	output [7:0] y2
-);
-	assign y1 = a + b + c + d;
-	assign y2 = e + f + g + h;
-endmodule
diff --git a/tests/csa_tree/add_wide_output.v b/tests/csa_tree/add_wide_output.v
deleted file mode 100644
index 1f0342777..000000000
--- a/tests/csa_tree/add_wide_output.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module add_wide_output(
-	input  [7:0] a, b, c, d,
-	output [31:0] y
-);
-	assign y = a + b + c + d;
-endmodule
diff --git a/tests/csa_tree/add_with_const.v b/tests/csa_tree/add_with_const.v
deleted file mode 100644
index 570a399e4..000000000
--- a/tests/csa_tree/add_with_const.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module add_with_const(
-	input  [7:0] a, b, c,
-	output [7:0] y
-);
-	assign y = a + b + c + 8'd42;
-endmodule
-
diff --git a/tests/csa_tree/csa_tree_16input.ys b/tests/csa_tree/csa_tree_16input.ys
deleted file mode 100644
index 46f51d44c..000000000
--- a/tests/csa_tree/csa_tree_16input.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_chain_16.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 14 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_1bit.ys b/tests/csa_tree/csa_tree_1bit.ys
deleted file mode 100644
index 4c1f7745a..000000000
--- a/tests/csa_tree/csa_tree_1bit.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_1bit.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 1 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_1bit_wide_out.ys b/tests/csa_tree/csa_tree_1bit_wide_out.ys
deleted file mode 100644
index 675fbc0a3..000000000
--- a/tests/csa_tree/csa_tree_1bit_wide_out.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_1bit_wide_out.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_2input_neg.ys b/tests/csa_tree/csa_tree_2input_neg.ys
deleted file mode 100644
index 810d1d8d9..000000000
--- a/tests/csa_tree/csa_tree_2input_neg.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-# Test csa_tree on 2-operand — should not trigger
-
-read_verilog add_chain_2_neg.v
-hierarchy -auto-top
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-
-select -assert-none t:$fa
-select -assert-count 1 t:$add
-
diff --git a/tests/csa_tree/csa_tree_3input.ys b/tests/csa_tree/csa_tree_3input.ys
deleted file mode 100644
index 9e7c9aaf2..000000000
--- a/tests/csa_tree/csa_tree_3input.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_chain_3.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 1 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_5input.ys b/tests/csa_tree/csa_tree_5input.ys
deleted file mode 100644
index ef26e21ce..000000000
--- a/tests/csa_tree/csa_tree_5input.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_chain_5.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_8input.ys b/tests/csa_tree/csa_tree_8input.ys
deleted file mode 100644
index fc5148edf..000000000
--- a/tests/csa_tree/csa_tree_8input.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_chain_8.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 6 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_add_chains.ys b/tests/csa_tree/csa_tree_add_chains.ys
new file mode 100644
index 000000000..46e5868a9
--- /dev/null
+++ b/tests/csa_tree/csa_tree_add_chains.ys
@@ -0,0 +1,61 @@
+read_verilog <<EOT
+module add3(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add5(
+	input [11:0] a, b, c, d, e,
+	output [11:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add8(
+	input [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add16(
+	input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [15:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
+	+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 14 t:$fa
+select -assert-count 1 t:$add
+design -reset
diff --git a/tests/csa_tree/csa_tree_const.ys b/tests/csa_tree/csa_tree_const.ys
deleted file mode 100644
index be53bba11..000000000
--- a/tests/csa_tree/csa_tree_const.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_with_const.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_edge_cases.ys b/tests/csa_tree/csa_tree_edge_cases.ys
new file mode 100644
index 000000000..1031f6c2c
--- /dev/null
+++ b/tests/csa_tree/csa_tree_edge_cases.ys
@@ -0,0 +1,147 @@
+read_verilog <<EOT
+module add_1bit(
+	input a, b, c,
+	output [1:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_1bit_wide(
+	input a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_wide_out(
+	input [7:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_mixed(
+	input [7:0] a,
+	input [3:0] b,
+	input [15:0] c,
+	input [7:0] d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_signed(
+	input signed [7:0] a, b, c, d,
+	output signed [9:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_repeated(
+	input [7:0] a,
+	output [7:0] y
+);
+	assign y = a + a + a + a;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_const(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c + 8'd42;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_two(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y1, y2
+);
+	assign y1 = a + b + c + d;
+	assign y2 = e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 4 t:$fa
+select -assert-count 2 t:$add
+design -reset
+
+read_verilog <<EOT
+module fir_4tap(
+	input clk,
+	input [15:0] x, c0, c1, c2, c3,
+	output reg [31:0] y
+);
+	reg [15:0] x1, x2, x3;
+	always @(posedge clk) begin
+		x1 <= x;
+		x2 <= x1;
+		x3 <= x2;
+	end
+
+	wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
+	always @(posedge clk) y <= sum;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
diff --git a/tests/csa_tree/csa_tree_equiv.ys b/tests/csa_tree/csa_tree_equiv.ys
index 360b9d30e..e208af6c8 100644
--- a/tests/csa_tree/csa_tree_equiv.ys
+++ b/tests/csa_tree/csa_tree_equiv.ys
@@ -1,81 +1,178 @@
-# Equivalence tests using narrow operands
-
-read_verilog equiv_narrow.v
-hierarchy -top equiv_add3
-proc; opt_clean
+read_verilog <<EOT
+module equiv_add3(
+	input [3:0] a, b, c,
+	output [3:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_add3"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_add4
-proc; opt_clean
+read_verilog <<EOT
+module equiv_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_add4"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_add5
-proc; opt_clean
+read_verilog <<EOT
+module equiv_add5(
+	input [3:0] a, b, c, d, e,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_add5"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_add8
-proc; opt_clean
+read_verilog <<EOT
+module equiv_add8(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_add8: ok"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_signed
-proc; opt_clean
+read_verilog <<EOT
+module equiv_signed(
+	input signed [3:0] a, b, c, d,
+	output signed [5:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_signed: ok"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_mixed_w
-proc; opt_clean
+read_verilog <<EOT
+module equiv_mixed(
+	input [1:0] a,
+	input [3:0] b,
+	input [5:0] c,
+	output [5:0] y
+);
+	assign y = a + b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_mixed_w: ok"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_repeated
-proc; opt_clean
+read_verilog <<EOT
+module equiv_sub_mixed(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_sub_all(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_sub_3op(
+	input [3:0] a, b, c,
+	output [3:0] y
+);
+	assign y = a - b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_repeated: ok"
 
-read_verilog equiv_narrow.v
-hierarchy -top equiv_1bit_wide
-proc; opt_clean
+read_verilog <<EOT
+module equiv_sub_signed(
+	input signed [3:0] a, b, c, d,
+	output signed [5:0] y
+);
+	assign y = a + b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt csa_tree
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module equiv_double_neg(
+	input [3:0] a, b, c,
+	output [3:0] y
+);
+	wire [3:0] ab = a - b;
+	assign y = c - ab;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 equiv_opt csa_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
-log "equiv_1bit_wide: ok"
diff --git a/tests/csa_tree/csa_tree_fir.ys b/tests/csa_tree/csa_tree_fir.ys
deleted file mode 100644
index 89d60af03..000000000
--- a/tests/csa_tree/csa_tree_fir.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog fir_4tap.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_idempotent.ys b/tests/csa_tree/csa_tree_idempotent.ys
index 138edb4ae..dfe098597 100644
--- a/tests/csa_tree/csa_tree_idempotent.ys
+++ b/tests/csa_tree/csa_tree_idempotent.ys
@@ -1,15 +1,19 @@
-read_verilog add_chain_8.v
+read_verilog <<EOT
+module add8(
+	input [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
 hierarchy -auto-top
-proc; opt_clean
+proc
 
 csa_tree
-stat
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 
 csa_tree
-stat
-
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_mixed_widths.ys b/tests/csa_tree/csa_tree_mixed_widths.ys
deleted file mode 100644
index e324c17ca..000000000
--- a/tests/csa_tree/csa_tree_mixed_widths.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_mixed_widths.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_multi_const.ys b/tests/csa_tree/csa_tree_multi_const.ys
deleted file mode 100644
index a68b60e33..000000000
--- a/tests/csa_tree/csa_tree_multi_const.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog add_multi_const.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-none t:$fa
-select -assert-max 1 t:$add
-
diff --git a/tests/csa_tree/csa_tree_multi_fanout.ys b/tests/csa_tree/csa_tree_multi_fanout.ys
deleted file mode 100644
index 0bce8d6bd..000000000
--- a/tests/csa_tree/csa_tree_multi_fanout.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_multi_fanout.v
-hierarchy -auto-top
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-
-select -assert-none t:$fa
-
diff --git a/tests/csa_tree/csa_tree_negative.ys b/tests/csa_tree/csa_tree_negative.ys
new file mode 100644
index 000000000..1cdcf3deb
--- /dev/null
+++ b/tests/csa_tree/csa_tree_negative.ys
@@ -0,0 +1,77 @@
+read_verilog <<EOT
+module add2(
+	input [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a + b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-none t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_fanout(
+	input [7:0] a, b, c,
+	output [7:0] mid, y
+);
+	wire [7:0] ab = a + b;
+	assign mid = ab;
+	assign y = ab + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-none t:$fa
+design -reset
+
+read_verilog <<EOT
+module sub2(
+	input [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a - b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-none t:$fa
+select -assert-count 1 t:$sub
+design -reset
+
+read_verilog <<EOT
+module add_multi_const(
+	input [7:0] x,
+	output [7:0] y
+);
+	assign y = 8'd1 + 8'd2 + 8'd3 + x;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-none t:$fa
+select -assert-max 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module add_partial(
+	input [7:0] a, b, c, d, e,
+	output [7:0] mid, y
+);
+	wire [7:0] ab = a + b;
+	assign mid = ab;
+	assign y = ab + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$add
+design -reset
diff --git a/tests/csa_tree/csa_tree_partial_chain.ys b/tests/csa_tree/csa_tree_partial_chain.ys
deleted file mode 100644
index ba857292e..000000000
--- a/tests/csa_tree/csa_tree_partial_chain.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_partial_chain.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 2 t:$add
diff --git a/tests/csa_tree/csa_tree_repeated.ys b/tests/csa_tree/csa_tree_repeated.ys
deleted file mode 100644
index b4581d2b4..000000000
--- a/tests/csa_tree/csa_tree_repeated.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_repeated.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_signed.ys b/tests/csa_tree/csa_tree_signed.ys
deleted file mode 100644
index 1093f7330..000000000
--- a/tests/csa_tree/csa_tree_signed.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_signed.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/csa_tree_sim.ys b/tests/csa_tree/csa_tree_sim.ys
index 5a571c268..7f6cbd1c8 100644
--- a/tests/csa_tree/csa_tree_sim.ys
+++ b/tests/csa_tree/csa_tree_sim.ys
@@ -1,23 +1,72 @@
-read_verilog sim_add4.v
-hierarchy -top sim_add4
-proc; opt_clean
+read_verilog <<EOT
+module sim_add4(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
 csa_tree
-opt_clean
 
-# 1 + 2 + 3 + 4 = 10
 sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
-
-# 0 + 0 + 0 + 0 = 0
 sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
-
-# 255 + 1 + 0 + 0 = 0
 sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
-
-# 100 + 50 + 25 + 25 = 200
 sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
-
-# 255 + 255 + 255 + 255 = 252
 sat -set a 255 -set b 255 -set c 255 -set d 255 -prove y 252
+design -reset
 
-log "ok"
+read_verilog <<EOT
+module sim_sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
 
+sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
+sat -set a 1 -set b 1 -set c 255 -set d 1 -prove y 4
+design -reset
+
+read_verilog <<EOT
+module sim_sub_all(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+
+sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252
+design -reset
+
+read_verilog <<EOT
+module sim_double_neg(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	wire [7:0] ab = a - b;
+	assign y = c - ab;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+
+sat -set a 30 -set b 20 -set c 10 -prove y 0
+sat -set a 50 -set b 25 -set c 100 -prove y 75
+sat -set a 0 -set b 0 -set c 0 -prove y 0
+sat -set a 255 -set b 1 -set c 1 -prove y 3
+design -reset
diff --git a/tests/csa_tree/csa_tree_sub_2op_neg.ys b/tests/csa_tree/csa_tree_sub_2op_neg.ys
deleted file mode 100644
index e2ee89a50..000000000
--- a/tests/csa_tree/csa_tree_sub_2op_neg.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog sub_2op_neg.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-none t:$fa
-select -assert-count 1 t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_3op.ys b/tests/csa_tree/csa_tree_sub_3op.ys
deleted file mode 100644
index 536f65bd7..000000000
--- a/tests/csa_tree/csa_tree_sub_3op.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog sub_3op.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 1 t:$not
-select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_5op.ys b/tests/csa_tree/csa_tree_sub_5op.ys
deleted file mode 100644
index b40c97084..000000000
--- a/tests/csa_tree/csa_tree_sub_5op.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog sub_5op.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 4 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 2 t:$not
-select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_all.ys b/tests/csa_tree/csa_tree_sub_all.ys
deleted file mode 100644
index ba0503462..000000000
--- a/tests/csa_tree/csa_tree_sub_all.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog sub_all.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 3 t:$not
-select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_chains.ys b/tests/csa_tree/csa_tree_sub_chains.ys
new file mode 100644
index 000000000..7f7ac1c34
--- /dev/null
+++ b/tests/csa_tree/csa_tree_sub_chains.ys
@@ -0,0 +1,102 @@
+read_verilog <<EOT
+module sub_3op(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a - b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 1 t:$not
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module sub_mixed(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b - c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 1 t:$not
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module sub_all(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 3 t:$not
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module sub_5op(
+	input [11:0] a, b, c, d, e,
+	output [11:0] y
+);
+	assign y = a - b + c - d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 4 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 2 t:$not
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module sub_signed(
+	input signed [7:0] a, b, c, d,
+	output signed [9:0] y
+);
+	assign y = a + b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 2 t:$not
+select -assert-none t:$sub
+design -reset
+
+read_verilog <<EOT
+module sub_double_neg(
+	input [7:0] a, b, c,
+	output [7:0] y
+);
+	wire [7:0] ab = a - b;
+	assign y = c - ab;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+csa_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 1 t:$not
+select -assert-none t:$sub
+design -reset
diff --git a/tests/csa_tree/csa_tree_sub_double_neg.ys b/tests/csa_tree/csa_tree_sub_double_neg.ys
deleted file mode 100644
index b3a524abb..000000000
--- a/tests/csa_tree/csa_tree_sub_double_neg.ys
+++ /dev/null
@@ -1,42 +0,0 @@
-read_verilog sub_double_neg.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 1 t:$not
-select -assert-none t:$sub
-
-design -reset
-
-# equiv_opt on narrow version
-read_verilog equiv_sub_double_neg.v
-hierarchy -top equiv_sub_double_neg
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog sub_double_neg.v
-hierarchy -top sub_double_neg
-proc; opt_clean
-csa_tree
-opt_clean
-
-# 10 - (30 - 20) = 0
-sat -set a 30 -set b 20 -set c 10 -prove y 0
-
-# 100 - (50 - 25) = 75
-sat -set a 50 -set b 25 -set c 100 -prove y 75
-
-# 0 - (0 - 0) = 0
-sat -set a 0 -set b 0 -set c 0 -prove y 0
-
-# 1 - (255 - 1) = 3
-sat -set a 255 -set b 1 -set c 1 -prove y 3
-
-log "double negation: ok"
diff --git a/tests/csa_tree/csa_tree_sub_equiv.ys b/tests/csa_tree/csa_tree_sub_equiv.ys
deleted file mode 100644
index 7138b010c..000000000
--- a/tests/csa_tree/csa_tree_sub_equiv.ys
+++ /dev/null
@@ -1,39 +0,0 @@
-read_verilog equiv_sub_narrow.v
-hierarchy -top equiv_sub_mixed
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-design -reset
-log "equiv_sub_mixed: ok"
-
-read_verilog equiv_sub_narrow.v
-hierarchy -top equiv_sub_all
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-design -reset
-log "equiv_sub_all: ok"
-
-read_verilog equiv_sub_narrow.v
-hierarchy -top equiv_sub_3op
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-design -reset
-log "equiv_sub_3op: ok"
-
-read_verilog equiv_sub_narrow.v
-hierarchy -top equiv_sub_signed
-proc; opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-design -reset
-log "equiv_sub_signed: ok"
diff --git a/tests/csa_tree/csa_tree_sub_mixed.ys b/tests/csa_tree/csa_tree_sub_mixed.ys
deleted file mode 100644
index 92e0e1a0d..000000000
--- a/tests/csa_tree/csa_tree_sub_mixed.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog sub_mixed.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 1 t:$not
-select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_signed.ys b/tests/csa_tree/csa_tree_sub_signed.ys
deleted file mode 100644
index ad3b0cfb4..000000000
--- a/tests/csa_tree/csa_tree_sub_signed.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog sub_signed.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 2 t:$not
-select -assert-none t:$sub
diff --git a/tests/csa_tree/csa_tree_sub_sim.ys b/tests/csa_tree/csa_tree_sub_sim.ys
deleted file mode 100644
index 73ca5f3e1..000000000
--- a/tests/csa_tree/csa_tree_sub_sim.ys
+++ /dev/null
@@ -1,38 +0,0 @@
-read_verilog sub_mixed.v
-hierarchy -top sub_mixed
-proc; opt_clean
-csa_tree
-opt_clean
-
-# 10 + 20 - 5 + 3 = 28
-sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
-
-# 0 + 0 - 0 + 0 = 0
-sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
-
-# 100 + 50 - 30 + 10 = 130
-sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
-
-# 1 + 1 - 255 + 1 = 4
-sat -set a 1 -set b 1 -set c 255 -set d 1 -prove y 4
-
-log "sub_mixed vectors: ok"
-
-design -reset
-
-read_verilog sub_all.v
-hierarchy -top sub_all
-proc; opt_clean
-csa_tree
-opt_clean
-
-# 100 - 10 - 20 - 30 = 40
-sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40
-
-# 0 - 0 - 0 - 0 = 0
-sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
-
-# 255 - 1 - 1 - 1 = 252
-sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252
-
-log "sub_all vectors: ok"
diff --git a/tests/csa_tree/csa_tree_synth.ys b/tests/csa_tree/csa_tree_synth.ys
index eb1e12a0f..2ed1fe32c 100644
--- a/tests/csa_tree/csa_tree_synth.ys
+++ b/tests/csa_tree/csa_tree_synth.ys
@@ -1,59 +1,70 @@
-# ABC synthesis comparison: with vs without csa_tree
-
-# Baseline: no csa_tree
-read_verilog abc_bench_add8.v
-hierarchy -top abc_bench_add8
-proc; opt
+# Assert against abc synth with and without csa, hopefully prevent regressions
+# Baseline
+read_verilog <<EOT
+module bench(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+opt
 techmap
 abc -g AND,OR,XOR
-opt_clean
-stat
-
-# Baseline is typically 238 gates — assert it's above 235
 select -assert-min 236 t:$_AND_ t:$_OR_ t:$_XOR_ %u
-
 design -reset
 
 # With csa_tree
-read_verilog abc_bench_add8.v
-hierarchy -top abc_bench_add8
-proc; opt
+read_verilog <<EOT
+module bench(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+opt
 csa_tree
 techmap
 abc -g AND,OR,XOR
-opt_clean
-stat
-
-# CSA was giving ~232 gates, assert rough equality
 select -assert-max 235 t:$_AND_ t:$_OR_ t:$_XOR_ %u
-
 design -reset
 
-# Depth-optimal: baseline
-read_verilog abc_bench_add8.v
-hierarchy -top abc_bench_add8
-proc; opt
+# Depth-otimal baseline
+read_verilog <<EOT
+module bench(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+opt
 techmap
 abc -D 1
-opt_clean
-stat
-
-# Baseline depth-optimal is  ~243 cells
 select -assert-min 240 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
-
 design -reset
 
-# Depth-optimal: with csa_tree
-read_verilog abc_bench_add8.v
-hierarchy -top abc_bench_add8
-proc; opt
+# Depth-optimal with csa_tree
+read_verilog <<EOT
+module bench(
+	input [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+opt
 csa_tree
 techmap
 abc -D 1
-opt_clean
-stat
-
-# CSA depth-optimal is ~232 cells, must be under baseline
 select -assert-max 236 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
-
-log "CSA depth and gate count: ok"
+design -reset
diff --git a/tests/csa_tree/csa_tree_two_chains.ys b/tests/csa_tree/csa_tree_two_chains.ys
deleted file mode 100644
index 42d5c87b9..000000000
--- a/tests/csa_tree/csa_tree_two_chains.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_two_chains.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 4 t:$fa
-select -assert-count 2 t:$add
diff --git a/tests/csa_tree/csa_tree_wide_output.ys b/tests/csa_tree/csa_tree_wide_output.ys
deleted file mode 100644
index ccb160f5c..000000000
--- a/tests/csa_tree/csa_tree_wide_output.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog add_wide_output.v
-hierarchy -auto-top
-proc; opt_clean
-csa_tree
-stat
-
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
diff --git a/tests/csa_tree/equiv_narrow.v b/tests/csa_tree/equiv_narrow.v
deleted file mode 100644
index f4f7ef279..000000000
--- a/tests/csa_tree/equiv_narrow.v
+++ /dev/null
@@ -1,59 +0,0 @@
-// Narrow-width test designs for SAT equivalence (4-bit to keep SAT fast)
-
-module equiv_add3(
-    input  [3:0] a, b, c,
-    output [3:0] y
-);
-    assign y = a + b + c;
-endmodule
-
-module equiv_add4(
-    input  [3:0] a, b, c, d,
-    output [3:0] y
-);
-    assign y = a + b + c + d;
-endmodule
-
-module equiv_add5(
-    input  [3:0] a, b, c, d, e,
-    output [3:0] y
-);
-    assign y = a + b + c + d + e;
-endmodule
-
-module equiv_add8(
-    input  [3:0] a, b, c, d, e, f, g, h,
-    output [3:0] y
-);
-    assign y = a + b + c + d + e + f + g + h;
-endmodule
-
-module equiv_signed(
-    input  signed [3:0] a, b, c, d,
-    output signed [5:0] y
-);
-    assign y = a + b + c + d;
-endmodule
-
-module equiv_mixed_w(
-    input  [1:0] a,
-    input  [3:0] b,
-    input  [5:0] c,
-    output [5:0] y
-);
-    assign y = a + b + c;
-endmodule
-
-module equiv_repeated(
-    input  [3:0] a,
-    output [3:0] y
-);
-    assign y = a + a + a + a;
-endmodule
-
-module equiv_1bit_wide(
-    input  a, b, c, d,
-    output [3:0] y
-);
-    assign y = a + b + c + d;
-endmodule
diff --git a/tests/csa_tree/equiv_sub_double_neg.v b/tests/csa_tree/equiv_sub_double_neg.v
deleted file mode 100644
index 8d03da23f..000000000
--- a/tests/csa_tree/equiv_sub_double_neg.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module equiv_sub_double_neg(
-	input  [3:0] a, b, c,
-	output [3:0] y
-);
-	wire [3:0] ab = a - b;
-	assign y = c - ab;
-endmodule
diff --git a/tests/csa_tree/equiv_sub_narrow.v b/tests/csa_tree/equiv_sub_narrow.v
deleted file mode 100644
index 3e40ee0bd..000000000
--- a/tests/csa_tree/equiv_sub_narrow.v
+++ /dev/null
@@ -1,27 +0,0 @@
-module equiv_sub_mixed(
-	input  [3:0] a, b, c, d,
-	output [3:0] y
-);
-	assign y = a + b - c + d;
-endmodule
-
-module equiv_sub_all(
-	input  [3:0] a, b, c, d,
-	output [3:0] y
-);
-	assign y = a - b - c - d;
-endmodule
-
-module equiv_sub_3op(
-	input  [3:0] a, b, c,
-	output [3:0] y
-);
-	assign y = a - b + c;
-endmodule
-
-module equiv_sub_signed(
-	input  signed [3:0] a, b, c, d,
-	output signed [5:0] y
-);
-	assign y = a + b - c - d;
-endmodule
diff --git a/tests/csa_tree/fir_4tap.v b/tests/csa_tree/fir_4tap.v
deleted file mode 100644
index 6c197dbd1..000000000
--- a/tests/csa_tree/fir_4tap.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module fir_4tap(
-	input         clk,
-	input  [15:0] x,
-	input  [15:0] c0, c1, c2, c3,
-	output reg [31:0] y
-);
-	reg [15:0] x1, x2, x3;
-	always @(posedge clk) begin
-		x1 <= x;
-		x2 <= x1;
-		x3 <= x2;
-	end
-
-	wire [31:0] p0 = x  * c0;
-	wire [31:0] p1 = x1 * c1;
-	wire [31:0] p2 = x2 * c2;
-	wire [31:0] p3 = x3 * c3;
-
-	wire [31:0] sum = p0 + p1 + p2 + p3;
-
-	always @(posedge clk)
-		y <= sum;
-endmodule
-
diff --git a/tests/csa_tree/run-test.sh b/tests/csa_tree/run-test.sh
index 2e3f5235c..0ef575c48 100755
--- a/tests/csa_tree/run-test.sh
+++ b/tests/csa_tree/run-test.sh
@@ -2,6 +2,6 @@
 source ../common-env.sh
 set -e
 for x in *.ys; do
-  echo "Running $x.."
-  ../../yosys -ql ${x%.ys}.log $x
+	echo "Running $x.."
+	../../yosys -ql ${x%.ys}.log $x
 done
diff --git a/tests/csa_tree/sim_add4.v b/tests/csa_tree/sim_add4.v
deleted file mode 100644
index 589044889..000000000
--- a/tests/csa_tree/sim_add4.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sim_add4(
-	input  [7:0] a, b, c, d,
-	output [7:0] y
-);
-	assign y = a + b + c + d;
-endmodule
diff --git a/tests/csa_tree/sub_2op_neg.v b/tests/csa_tree/sub_2op_neg.v
deleted file mode 100644
index 33a320cef..000000000
--- a/tests/csa_tree/sub_2op_neg.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_2op_neg(
-	input  [7:0] a, b,
-	output [7:0] y
-);
-	assign y = a - b;
-endmodule
diff --git a/tests/csa_tree/sub_3op.v b/tests/csa_tree/sub_3op.v
deleted file mode 100644
index 270605e6f..000000000
--- a/tests/csa_tree/sub_3op.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_3op(
-	input  [7:0] a, b, c,
-	output [7:0] y
-);
-	assign y = a - b + c;
-endmodule
diff --git a/tests/csa_tree/sub_5op.v b/tests/csa_tree/sub_5op.v
deleted file mode 100644
index 1c18adab0..000000000
--- a/tests/csa_tree/sub_5op.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_5op(
-	input  [11:0] a, b, c, d, e,
-	output [11:0] y
-);
-	assign y = a - b + c - d + e;
-endmodule
diff --git a/tests/csa_tree/sub_all.v b/tests/csa_tree/sub_all.v
deleted file mode 100644
index 33897159d..000000000
--- a/tests/csa_tree/sub_all.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_all(
-	input  [7:0] a, b, c, d,
-	output [7:0] y
-);
-	assign y = a - b - c - d;
-endmodule
diff --git a/tests/csa_tree/sub_double_neg.v b/tests/csa_tree/sub_double_neg.v
deleted file mode 100644
index 7172ccd09..000000000
--- a/tests/csa_tree/sub_double_neg.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module sub_double_neg(
-	input  [7:0] a, b, c,
-	output [7:0] y
-);
-	wire [7:0] ab = a - b;
-	assign y = c - ab;
-endmodule
diff --git a/tests/csa_tree/sub_mixed.v b/tests/csa_tree/sub_mixed.v
deleted file mode 100644
index f711da3fc..000000000
--- a/tests/csa_tree/sub_mixed.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_mixed(
-	input  [7:0] a, b, c, d,
-	output [7:0] y
-);
-	assign y = a + b - c + d;
-endmodule
diff --git a/tests/csa_tree/sub_signed.v b/tests/csa_tree/sub_signed.v
deleted file mode 100644
index 6971840ab..000000000
--- a/tests/csa_tree/sub_signed.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module sub_signed(
-	input  signed [7:0] a, b, c, d,
-	output signed [9:0] y
-);
-	assign y = a + b - c - d;
-endmodule