mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

update documentation for enums and typedefs

Browse source
This commit is contained in:
Jeff Wang 2020-02-17 04:40:18 -05:00 committed by Jeff Wang
parent a31ba8e5d5
commit 1c16311d10
1 changed files with 17 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
README.md
View file

@ -437,6 +437,17 @@ Verilog Attributes and non-standard features
... ...
endmodule endmodule
- The ``wiretype`` attribute is added by the verilog parser for wires of a
typedef'd type to indicate the type identifier.
- Various ``enum_{width}_{value}`` attributes are added to wires of an
enumerated type to give a map of possible enum items to their values.
- The ``enum_base_type`` attribute is added to enum items to indicate which
enum they belong to (enums -- anonymous and otherwise -- are
automatically named with an auto-incrementing counter). Note that enums
are currently not strongly typed.
- A limited subset of DPI-C functions is supported. The plugin mechanism - A limited subset of DPI-C functions is supported. The plugin mechanism
(see ``help plugin``) can be used to load .so files with implementations (see ``help plugin``) can be used to load .so files with implementations
of DPI-C routines. As a non-standard extension it is possible to specify of DPI-C routines. As a non-standard extension it is possible to specify
@ -527,6 +538,12 @@ from SystemVerilog:
SystemVerilog files being read into the same design afterwards. SystemVerilog files being read into the same design afterwards.
- typedefs are supported (including inside packages) - typedefs are supported (including inside packages)
- type identifiers must currently be enclosed in (parentheses) when declaring
signals of that type (this is syntactically incorrect SystemVerilog)
- type casts are currently not supported
- enums are supported (including inside packages)
- but are currently not strongly typed
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported. ports are inputs or outputs are supported.