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Do not replace constants with same wire

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This commit is contained in:
Eddie Hung 2019-11-27 08:18:41 -08:00
parent c7aa2c6b79
commit 1c0ee4f786
1 changed files with 3 additions and 7 deletions
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10
passes/hierarchy/submod.cc
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@ -34,7 +34,6 @@ struct SubmodWorker
RTLIL::Design *design; RTLIL::Design *design;
RTLIL::Module *module; RTLIL::Module *module;
SigMap sigmap; SigMap sigmap;
std::map<RTLIL::SigBit, RTLIL::SigBit> replace_const;
bool copy_mode; bool copy_mode;
bool hidden_mode; bool hidden_mode;
@ -231,7 +230,9 @@ struct SubmodWorker
if (new_wire->port_id > 0) { if (new_wire->port_id > 0) {
// Prevents "ERROR: Mismatch in directionality ..." when flattening // Prevents "ERROR: Mismatch in directionality ..." when flattening
if (new_wire->port_output) if (new_wire->port_output)
old_sig.replace(replace_const); for (auto &b : old_sig)
if (!b.wire)
b = module->addWire(NEW_ID);
new_cell->setPort(new_wire->name, old_sig); new_cell->setPort(new_wire->name, old_sig);
} }
} }
@ -265,11 +266,6 @@ struct SubmodWorker
if (wire->port_output) if (wire->port_output)
sigmap.add(wire); sigmap.add(wire);
} }
auto wire = module->addWire(NEW_ID);
replace_const.emplace(State::S0, wire);
replace_const.emplace(State::S1, wire);
replace_const.emplace(State::Sx, wire);
replace_const.emplace(State::Sz, wire);
if (opt_name.empty()) if (opt_name.empty())
{ {