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Added module->ports

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This commit is contained in:
Clifford Wolf 2014-08-14 16:13:42 +02:00
parent 746aac540b
commit 1bf7a18fec
9 changed files with 23 additions and 10 deletions
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4
passes/techmap/extract.cc
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@ -726,14 +726,14 @@ struct ExtractPass : public Pass {
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
map->add(newMod);
int portCounter = 1;
for (auto wire : wires) {
RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
newWire->port_id = portCounter++;
newWire->port_input = true;
newWire->port_output = true;
}
newMod->fixup_ports();
for (auto cell : cells) {
RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
newCell->parameters = cell->parameters;