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Added module->ports

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This commit is contained in:
Clifford Wolf 2014-08-14 16:13:42 +02:00
parent 746aac540b
commit 1bf7a18fec
9 changed files with 23 additions and 10 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
wire->port_output = decl.output;
}
mod->fixup_ports();
for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));