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Added module->ports

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This commit is contained in:
Clifford Wolf 2014-08-14 16:13:42 +02:00
parent 746aac540b
commit 1bf7a18fec
9 changed files with 23 additions and 10 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
wire->port_output = decl.output;
}
mod->fixup_ports();
for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));

7
passes/hierarchy/submod.cc
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@ -106,7 +106,7 @@ struct SubmodWorker
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->name = submod.full_name;
design->add(new_mod);
int port_counter = 1, auto_name_counter = 1;
int auto_name_counter = 1;
std::set<RTLIL::IdString> all_wire_names;
for (auto &it : wire_flags) {
@ -151,9 +151,6 @@ struct SubmodWorker
new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
if (new_wire->port_input || new_wire->port_output)
new_wire->port_id = port_counter++;
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
else if (new_wire->port_input)
@ -166,6 +163,8 @@ struct SubmodWorker
flags.new_wire = new_wire;
}
new_mod->fixup_ports();
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
for (auto &conn : new_cell->connections_)