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Added module->ports

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This commit is contained in:
Clifford Wolf 2014-08-14 16:13:42 +02:00
parent 746aac540b
commit 1bf7a18fec
9 changed files with 23 additions and 10 deletions
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3
passes/abc/blifparse.cc
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@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
RTLIL::Const *lutptr = NULL;
RTLIL::State lut_default_state = RTLIL::State::Sx;
int port_count = 0;
module->name = "\\netlist";
design->add(module);
@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
continue;
if (!strcmp(cmd, ".end")) {
module->fixup_ports();
free(buffer);
return design;
}
@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
char *p;
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
wire->port_id = ++port_count;
if (!strcmp(cmd, ".inputs"))
wire->port_input = true;
else