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Added module->ports

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This commit is contained in:
Clifford Wolf 2014-08-14 16:13:42 +02:00
parent 746aac540b
commit 1bf7a18fec
9 changed files with 23 additions and 10 deletions
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3
kernel/celltypes.h
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@ -67,7 +67,8 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
std::set<RTLIL::IdString> inputs, outputs;
for (auto wire : module->wires()) {
for (RTLIL::IdString wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->name);
if (wire->port_output)