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Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup

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opt_merge: speedup
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Eddie Hung 2020-03-31 14:50:32 -07:00 • committed by GitHub
commit 1bb5a5215f
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3 changed files with 189 additions and 127 deletions
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28
tests/opt/opt_merge_init.ys
View file

@ -20,6 +20,7 @@ endmodule
EOT
opt_merge
select -assert-count 1 t:$dff
select -assert-count 1 a:init=1'0
@ -46,4 +47,31 @@ endmodule
EOT
opt_merge
select -assert-count 1 t:$dff
select -assert-count 1 a:init=2'bx1
design -reset
read_verilog -icells <<EOT
module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffo (
.CLK(clk),
.D(i),
.Q(o)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffp (
.CLK(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 2 t:$dff

64
tests/opt/opt_merge_keep.ys Normal file
View file

@ -0,0 +1,64 @@
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* keep *)
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 a:keep
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
(* keep *)
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 a:keep
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* keep *)
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
(* keep *)
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 2 t:$_DFF_P_
select -assert-count 2 a:keep