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Only toposort builtin and abc types

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This commit is contained in:
Eddie Hung 2019-06-04 11:56:58 -07:00
parent 82d41bc2f2
commit 1b836c93bb
1 changed files with 9 additions and 6 deletions
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15
backends/aiger/xaiger.cc
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@ -181,14 +181,17 @@ struct XAigerWriter
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
RTLIL::Module* inst_module = module->design->module(cell->type); RTLIL::Module* inst_module = module->design->module(cell->type);
bool known_type = yosys_celltypes.cell_known(cell->type); bool builtin_type = yosys_celltypes.cell_known(cell->type);
bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id");
if (!holes_mode) { if (!holes_mode) {
toposort.node(cell->name); toposort.node(cell->name);
for (const auto &conn : cell->connections()) for (const auto &conn : cell->connections()) {
{ if (!builtin_type && !abc_type)
continue;
if (!cell->type.in("$_NOT_", "$_AND_")) { if (!cell->type.in("$_NOT_", "$_AND_")) {
if (known_type) { if (builtin_type) {
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
continue; continue;
if (cell->type == "$memrd" && conn.first == "\\DATA") if (cell->type == "$memrd" && conn.first == "\\DATA")
@ -199,8 +202,8 @@ struct XAigerWriter
RTLIL::Wire* inst_module_port = inst_module->wire(conn.first); RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
log_assert(inst_module_port); log_assert(inst_module_port);
if (inst_module_port->attributes.count("\\abc_flop_q")) if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q"))
continue; continue;
} }
} }