mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
memory_libmap: look for ram_style attributes on surrounding signals
This commit is contained in:
parent
d21c464ae4
commit
1b6d1e9419
5 changed files with 146 additions and 5 deletions
|
@ -140,6 +140,7 @@ X(nomem2reg)
|
|||
X(nomeminit)
|
||||
X(nosync)
|
||||
X(nowrshmsk)
|
||||
X(no_ram)
|
||||
X(no_rw_check)
|
||||
X(O)
|
||||
X(OFFSET)
|
||||
|
|
|
@ -148,6 +148,8 @@ void Mem::emit() {
|
|||
for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++)
|
||||
wr_port_xlat.push_back(i);
|
||||
for (auto &port : rd_ports) {
|
||||
for (auto attr: port.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (port.cell) {
|
||||
module->remove(port.cell);
|
||||
port.cell = nullptr;
|
||||
|
@ -210,6 +212,8 @@ void Mem::emit() {
|
|||
cell->setPort(ID::RD_ADDR, rd_addr);
|
||||
cell->setPort(ID::RD_DATA, rd_data);
|
||||
for (auto &port : wr_ports) {
|
||||
for (auto attr: port.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (port.cell) {
|
||||
module->remove(port.cell);
|
||||
port.cell = nullptr;
|
||||
|
@ -246,6 +250,8 @@ void Mem::emit() {
|
|||
cell->setPort(ID::WR_ADDR, wr_addr);
|
||||
cell->setPort(ID::WR_DATA, wr_data);
|
||||
for (auto &init : inits) {
|
||||
for (auto attr: init.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (init.cell) {
|
||||
module->remove(init.cell);
|
||||
init.cell = nullptr;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue