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A_SIGNED == B_SIGNED so flip both

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This commit is contained in:
Eddie Hung 2019-07-17 11:34:18 -07:00
parent d63f105708
commit 1b62b82e05
1 changed files with 12 additions and 21 deletions
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31
techlibs/common/mul2dsp.v
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@ -34,31 +34,22 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED;
localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED;
if (add_sign_A || add_sign_B) begin
if (add_sign_A && add_sign_B)
wire [1:0] dummy;
else
wire dummy; wire dummy;
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH+1),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH+1)
) _TECHMAP_REPLACE_ (
.A({1'b0, A}),
.B(B),
.Y({dummy, Y})
);
end
else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin
wire dummy;
\$mul #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)),
.B_WIDTH(B_WIDTH+1), .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)),
.Y_WIDTH(Y_WIDTH+1) .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0))
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(add_sign_A ? {1'b0, A} : A),
.B({1'b0, B}), .B(add_sign_B ? {1'b0, B} : B),
.Y({dummy, Y}) .Y({dummy, Y})
); );
end end