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Reduced log verbosity

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This commit is contained in:
Andrew Zonenberg 2016-03-30 22:03:50 -07:00
parent ad19e0c64a
commit 1b42e0c471
1 changed files with 8 additions and 9 deletions
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17
passes/techmap/counters.cc
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@ -202,13 +202,12 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i
//Log it //Log it
total_counters ++; total_counters ++;
log(" Extracting %d-bit counter to %s hard macro\n", a_width, celltype.c_str()); string count_reg_src = rwire->attributes["\\src"].decode_string().c_str();
log(" Decrementer: %s\n", cell->name.c_str()); log(" Found %d-bit non-resettable down counter (from %d) for register %s declared at %s\n",
log(" Output mux: %s\n", count_mux->name.c_str()); a_width,
log(" Register: %s\n", count_reg->name.c_str()); count_value,
log(" Comparator: %s\n", underflow_inv->name.c_str()); log_id(rwire->name),
log(" Count value: %d\n", count_value); count_reg_src.c_str());
/* /*
log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
@ -240,12 +239,12 @@ struct CountersPass : public Pass {
log("\n"); log("\n");
log(" counters [options] [selection]\n"); log(" counters [options] [selection]\n");
log("\n"); log("\n");
log("This pass converts resettable down counters to GreenPak counter cells\n"); log("This pass converts resettable down counters to GreenPak4 counter cells\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing COUNTERS pass (mapping counters to GP_COUNTx cells).\n"); log_header("Executing COUNTERS pass (mapping counters to hard IP blocks).\n");
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)