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Akash Levy 2025-09-09 05:50:48 -07:00
parent 36b753285c
commit 1b3375d8df
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2
tests/verilog/unbased_unsized_shift.ys
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@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all