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117 changed files with 1890 additions and 984 deletions
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@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
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else
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{
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
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apply_attrs(eq_cell, sw, cs);
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eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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