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Merge pull request #4525 from georgerennie/peepopt_clock_gate

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peepopt: Add formal opt to rewrite latches to ffs in clock gates
This commit is contained in:
Martin Povišer 2024-11-11 14:49:09 +01:00 • committed by GitHub
commit 1b1a6c4aed
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5 changed files with 141 additions and 5 deletions
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15
passes/sat/clk2fflogic.cc
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@ -51,6 +51,10 @@ struct Clk2fflogicPass : public Pass {
log(" -nolower\n");
log(" Do not automatically run 'chformal -lower' to lower $check cells.\n");
log("\n");
log(" -nopeepopt\n");
log(" Do not automatically run 'peepopt -formalclk' to rewrite clock patterns\n");
log(" to more formal friendly forms.\n");
log("\n");
}
// Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted.
SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
@ -121,6 +125,7 @@ struct Clk2fflogicPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nolower = false;
bool flag_nopeepopt = false;
log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
@ -131,10 +136,20 @@ struct Clk2fflogicPass : public Pass {
flag_nolower = true;
continue;
}
if (args[argidx] == "-nopeepopt") {
flag_nopeepopt = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!flag_nopeepopt) {
log_push();
Pass::call(design, "peepopt -formalclk");
log_pop();
}
bool have_check_cells = false;
for (auto module : design->selected_modules())