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Reduce verbosity of some key things

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This commit is contained in:
Akash Levy 2025-03-04 22:58:56 -08:00
parent 47246954d4
commit 1b1855353d
4 changed files with 26 additions and 26 deletions
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2
passes/techmap/extract_reduce.cc
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@ -277,7 +277,7 @@ struct ExtractReducePass : public Pass
if (inner_cells)
{
// Worth it to create reduce cell
log("Creating reduce_* cell for %s (%s) in %s\n", head_cell->name.c_str(), head_cell->type.c_str(), module->name.c_str());
log_debug("Creating reduce_* cell for %s (%s) in %s\n", head_cell->name.c_str(), head_cell->type.c_str(), module->name.c_str());
SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);