mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Added cover() calls to RTLIL::SigSpec methods
This commit is contained in:
Clifford Wolf
parent
9cf12570ba
commit
1b0d5fc22d
1 changed files with 93 additions and 5 deletions
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@ -1516,6 +1516,7 @@ void RTLIL::SigSpec::pack() const
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if (that->bits_.empty())
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return;
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cover("kernel.rtlil.sigspec.pack");
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log_assert(that->chunks_.empty());
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std::vector<RTLIL::SigBit> old_bits;
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@ -1533,6 +1534,7 @@ void RTLIL::SigSpec::unpack() const
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if (that->chunks_.empty())
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return;
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cover("kernel.rtlil.sigspec.unpack");
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log_assert(that->bits_.empty());
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that->bits_.reserve(that->width_);
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@ -1553,9 +1555,10 @@ void RTLIL::SigSpec::hash() const
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if (that->hash_ != 0)
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return;
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cover("kernel.rtlil.sigspec.hash");
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that->pack();
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that->hash_ = 5381;
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that->hash_ = 5381;
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for (auto &c : that->chunks_)
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if (c.wire == NULL) {
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for (auto &v : c.data.bits)
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@ -1574,11 +1577,13 @@ void RTLIL::SigSpec::hash() const
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void RTLIL::SigSpec::sort()
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{
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unpack();
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cover("kernel.rtlil.sigspec.sort");
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std::sort(bits_.begin(), bits_.end());
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}
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void RTLIL::SigSpec::sort_and_unify()
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{
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cover("kernel.rtlil.sigspec.sort_and_unify");
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*this = this->to_sigbit_set();
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}
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@ -1589,6 +1594,11 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
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{
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if (other)
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cover("kernel.rtlil.sigspec.replace_other");
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else
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cover("kernel.rtlil.sigspec.replace");
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unpack();
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pattern.unpack();
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with.unpack();
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@ -1624,6 +1634,11 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other
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void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
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{
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if (other)
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cover("kernel.rtlil.sigspec.remove_other");
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else
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cover("kernel.rtlil.sigspec.remove");
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unpack();
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if (other != NULL) {
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@ -1655,6 +1670,11 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
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RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const
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{
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if (other)
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cover("kernel.rtlil.sigspec.extract_other");
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else
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cover("kernel.rtlil.sigspec.extract");
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pack();
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pattern.pack();
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@ -1684,6 +1704,8 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o
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void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
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{
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cover("kernel.rtlil.sigspec.replace");
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unpack();
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with.unpack();
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@ -1699,6 +1721,8 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
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void RTLIL::SigSpec::remove_const()
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{
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cover("kernel.rtlil.sigspec.remove_const");
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unpack();
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std::vector<RTLIL::SigBit> new_bits;
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@ -1716,6 +1740,8 @@ void RTLIL::SigSpec::remove_const()
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void RTLIL::SigSpec::remove(int offset, int length)
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{
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cover("kernel.rtlil.sigspec.remove_pos");
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unpack();
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assert(offset >= 0);
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@ -1731,6 +1757,7 @@ void RTLIL::SigSpec::remove(int offset, int length)
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RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
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{
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unpack();
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cover("kernel.rtlil.sigspec.extract_pos");
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return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
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}
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@ -1744,6 +1771,8 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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return;
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}
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cover("kernel.rtlil.sigspec.append");
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if (packed() != signal.packed()) {
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pack();
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signal.pack();
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@ -1776,6 +1805,8 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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{
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if (packed())
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{
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cover("kernel.rtlil.sigspec.append_bit.packed");
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if (chunks_.size() == 0)
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chunks_.push_back(bit);
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else
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@ -1792,7 +1823,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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chunks_.push_back(bit);
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}
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else
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{
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cover("kernel.rtlil.sigspec.append_bit.unpacked");
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bits_.push_back(bit);
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}
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width_++;
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@ -1801,6 +1835,8 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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void RTLIL::SigSpec::extend(int width, bool is_signed)
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{
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cover("kernel.rtlil.sigspec.extend");
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pack();
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if (width_ > width)
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@ -1818,6 +1854,8 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
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void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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{
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cover("kernel.rtlil.sigspec.extend_0");
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pack();
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if (width_ > width)
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@ -1835,6 +1873,8 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
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{
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cover("kernel.rtlil.sigspec.repeat");
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RTLIL::SigSpec sig;
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for (int i = 0; i < num; i++)
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sig.append(*this);
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@ -1846,6 +1886,8 @@ void RTLIL::SigSpec::check() const
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#ifndef NDEBUG
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if (packed())
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{
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cover("kernel.rtlil.sigspec.check.packed");
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int w = 0;
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for (size_t i = 0; i < chunks_.size(); i++) {
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const RTLIL::SigChunk chunk = chunks_[i];
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@ -1869,6 +1911,8 @@ void RTLIL::SigSpec::check() const
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}
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else
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{
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cover("kernel.rtlil.sigspec.check.unpacked");
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assert(width_ == SIZE(bits_));
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assert(chunks_.empty());
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}
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@ -1877,6 +1921,8 @@ void RTLIL::SigSpec::check() const
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bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
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{
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cover("kernel.rtlil.sigspec.comp_lt");
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if (this == &other)
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return false;
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@ -1896,14 +1942,18 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
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return hash_ < other.hash_;
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for (size_t i = 0; i < chunks_.size(); i++)
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if (chunks_[i] != other.chunks_[i])
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if (chunks_[i] != other.chunks_[i]) {
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cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
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return chunks_[i] < other.chunks_[i];
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}
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return false;
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}
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bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
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{
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cover("kernel.rtlil.sigspec.comp_eq");
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if (this == &other)
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return true;
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@ -1923,14 +1973,18 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
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return false;
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for (size_t i = 0; i < chunks_.size(); i++)
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if (chunks_[i] != other.chunks_[i])
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if (chunks_[i] != other.chunks_[i]) {
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cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
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return false;
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}
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return true;
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}
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bool RTLIL::SigSpec::is_fully_const() const
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{
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cover("kernel.rtlil.sigspec.is_fully_const");
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pack();
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for (auto it = chunks_.begin(); it != chunks_.end(); it++)
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if (it->width > 0 && it->wire != NULL)
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@ -1940,6 +1994,8 @@ bool RTLIL::SigSpec::is_fully_const() const
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bool RTLIL::SigSpec::is_fully_def() const
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{
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cover("kernel.rtlil.sigspec.is_fully_def");
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pack();
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for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
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if (it->width > 0 && it->wire != NULL)
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@ -1953,6 +2009,8 @@ bool RTLIL::SigSpec::is_fully_def() const
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bool RTLIL::SigSpec::is_fully_undef() const
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{
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cover("kernel.rtlil.sigspec.is_fully_undef");
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pack();
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for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
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if (it->width > 0 && it->wire != NULL)
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@ -1966,6 +2024,8 @@ bool RTLIL::SigSpec::is_fully_undef() const
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bool RTLIL::SigSpec::has_marked_bits() const
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{
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cover("kernel.rtlil.sigspec.has_marked_bits");
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pack();
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for (auto it = chunks_.begin(); it != chunks_.end(); it++)
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if (it->width > 0 && it->wire == NULL) {
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@ -1978,6 +2038,8 @@ bool RTLIL::SigSpec::has_marked_bits() const
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bool RTLIL::SigSpec::as_bool() const
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{
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cover("kernel.rtlil.sigspec.as_bool");
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pack();
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assert(is_fully_const() && SIZE(chunks_) <= 1);
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if (width_)
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@ -1987,6 +2049,8 @@ bool RTLIL::SigSpec::as_bool() const
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int RTLIL::SigSpec::as_int() const
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{
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cover("kernel.rtlil.sigspec.as_int");
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pack();
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assert(is_fully_const() && SIZE(chunks_) <= 1);
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if (width_)
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@ -1996,6 +2060,8 @@ int RTLIL::SigSpec::as_int() const
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std::string RTLIL::SigSpec::as_string() const
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{
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cover("kernel.rtlil.sigspec.as_string");
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pack();
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std::string str;
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for (size_t i = chunks_.size(); i > 0; i--) {
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@ -2011,6 +2077,8 @@ std::string RTLIL::SigSpec::as_string() const
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RTLIL::Const RTLIL::SigSpec::as_const() const
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{
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cover("kernel.rtlil.sigspec.as_const");
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pack();
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assert(is_fully_const() && SIZE(chunks_) <= 1);
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if (width_)
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@ -2020,6 +2088,8 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
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bool RTLIL::SigSpec::match(std::string pattern) const
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{
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cover("kernel.rtlil.sigspec.match");
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pack();
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std::string str = as_string();
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assert(pattern.size() == str.size());
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@ -2041,6 +2111,8 @@ bool RTLIL::SigSpec::match(std::string pattern) const
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std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
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{
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cover("kernel.rtlil.sigspec.to_sigbit_set");
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pack();
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std::set<RTLIL::SigBit> sigbits;
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for (auto &c : chunks_)
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@ -2051,12 +2123,16 @@ std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
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std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
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{
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cover("kernel.rtlil.sigspec.to_sigbit_vector");
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unpack();
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return bits_;
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}
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RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
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{
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cover("kernel.rtlil.sigspec.to_single_sigbit");
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pack();
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log_assert(width_ == 1);
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for (auto &c : chunks_)
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@ -2082,6 +2158,8 @@ static int sigspec_parse_get_dummy_line_num()
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bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
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{
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cover("kernel.rtlil.sigspec.parse");
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std::vector<std::string> tokens;
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sigspec_parse_split(tokens, str, ',');
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@ -2095,6 +2173,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
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continue;
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if ('0' <= netname[0] && netname[0] <= '9') {
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cover("kernel.rtlil.sigspec.parse.const");
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AST::get_line_num = sigspec_parse_get_dummy_line_num;
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AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
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if (ast == NULL)
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@ -2107,6 +2186,8 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
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if (module == NULL)
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return false;
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cover("kernel.rtlil.sigspec.parse.net");
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if (netname[0] != '$' && netname[0] != '\\')
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netname = "\\" + netname;
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@ -2134,9 +2215,11 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
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if (!indices.empty()) {
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std::vector<std::string> index_tokens;
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sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
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if (index_tokens.size() == 1)
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if (index_tokens.size() == 1) {
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cover("kernel.rtlil.sigspec.parse.bit_sel");
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sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
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else {
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} else {
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cover("kernel.rtlil.sigspec.parse.part_sel");
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int a = atoi(index_tokens.at(0).c_str());
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int b = atoi(index_tokens.at(1).c_str());
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if (a > b) {
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@ -2157,6 +2240,8 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL
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if (str.empty() || str[0] != '@')
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return parse(sig, module, str);
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cover("kernel.rtlil.sigspec.parse.sel");
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str = RTLIL::escape_id(str.substr(1));
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if (design->selection_vars.count(str) == 0)
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return false;
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@ -2173,11 +2258,13 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL
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bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
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{
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if (str == "0") {
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cover("kernel.rtlil.sigspec.parse.rhs_zeros");
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sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
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return true;
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}
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if (str == "~0") {
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cover("kernel.rtlil.sigspec.parse.rhs_ones");
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sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
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return true;
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}
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@ -2187,6 +2274,7 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
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long long int val = strtoll(p, &endptr, 10);
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if (endptr && endptr != p && *endptr == 0) {
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sig = RTLIL::SigSpec(val, lhs.width_);
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cover("kernel.rtlil.sigspec.parse.rhs_dec");
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return true;
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}
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}
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