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https://github.com/YosysHQ/yosys
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Improved opt_reduce handling of mem wr_en mux bits
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parent
274c514879
commit
1b00861d0a
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@ -186,11 +186,21 @@ struct OptReduceWorker
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for (int i = 0; i < int(sig_y.size()); i++)
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for (int i = 0; i < int(sig_y.size()); i++)
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{
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{
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std::vector<RTLIL::SigBit> in_tuple;
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std::vector<RTLIL::SigBit> in_tuple;
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in_tuple.push_back(sig_a.at(i));
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bool all_tuple_bits_same = true;
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for (int j = i; j < int(sig_b.size()); j += int(sig_a.size()))
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in_tuple.push_back(sig_b.at(j));
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if (consolidated_in_tuples_map.count(in_tuple))
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in_tuple.push_back(sig_a.at(i));
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for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) {
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if (sig_b.at(j) != sig_a.at(i))
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all_tuple_bits_same = false;
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in_tuple.push_back(sig_b.at(j));
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}
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if (all_tuple_bits_same)
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{
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old_sig_conn.first.append_bit(sig_y.at(i));
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old_sig_conn.second.append_bit(sig_a.at(i));
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}
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else if (consolidated_in_tuples_map.count(in_tuple))
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{
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{
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old_sig_conn.first.append_bit(sig_y.at(i));
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old_sig_conn.first.append_bit(sig_y.at(i));
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old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
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old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
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@ -206,7 +216,8 @@ struct OptReduceWorker
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if (new_sig_y.size() != sig_y.size())
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if (new_sig_y.size() != sig_y.size())
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{
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{
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log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
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log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
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log(" Old inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"]));
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log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
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log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
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cell->connections["\\A"] = RTLIL::SigSpec();
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cell->connections["\\A"] = RTLIL::SigSpec();
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for (auto &in_tuple : consolidated_in_tuples)
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for (auto &in_tuple : consolidated_in_tuples)
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@ -217,11 +228,13 @@ struct OptReduceWorker
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for (auto &in_tuple : consolidated_in_tuples)
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for (auto &in_tuple : consolidated_in_tuples)
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cell->connections["\\B"].append(in_tuple.at(i));
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cell->connections["\\B"].append(in_tuple.at(i));
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log(" New inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"]));
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cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
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cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
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cell->connections["\\Y"] = new_sig_y;
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cell->connections["\\Y"] = new_sig_y;
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log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
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log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
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log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
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module->connections.push_back(old_sig_conn);
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module->connections.push_back(old_sig_conn);
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module->check();
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module->check();
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