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https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
AigMaker refactoring
This commit is contained in:
Clifford Wolf
parent
e534881794
commit
1ae360cf72
4 changed files with 165 additions and 90 deletions
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@ -225,7 +225,7 @@ struct JsonWriter
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f << stringf("\"%sport\", \"%s\", %d", node.inverter ? "n" : "",
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log_id(node.portname), node.portbit);
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else if (node.left_parent < 0 && node.right_parent < 0)
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f << stringf("\"%s\"", node.inverter ? "false" : "true");
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f << stringf("\"%s\"", node.inverter ? "true" : "false");
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else
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f << stringf("\"%s\", %d, %d", node.inverter ? "nand" : "and", node.left_parent, node.right_parent);
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for (auto &op : node.outports)
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@ -21,6 +21,14 @@
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YOSYS_NAMESPACE_BEGIN
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AigNode::AigNode()
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{
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portbit = -1;
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inverter = false;
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left_parent = -1;
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right_parent = -1;
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}
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bool AigNode::operator==(const AigNode &other) const
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{
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if (portname != other.portname) return false;
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@ -66,13 +74,13 @@ struct AigMaker
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the_false_node = -1;
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}
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int bool_node(bool value)
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int node2index(const AigNode &node)
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{
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AigNode node;
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node.portbit = -1;
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node.inverter = !value;
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node.left_parent = -1;
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node.right_parent = -1;
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if (node.left_parent > node.right_parent) {
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AigNode n(node);
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std::swap(n.left_parent, n.right_parent);
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return node2index(n);
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}
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if (!aig_indices.count(node)) {
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aig_indices.expect(node, GetSize(aig->nodes));
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@ -82,6 +90,13 @@ struct AigMaker
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return aig_indices.at(node);
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}
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int bool_node(bool value)
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{
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AigNode node;
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node.inverter = value;
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return node2index(node);
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}
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int inport(IdString portname, int portbit = 0, bool inverter = false)
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{
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if (portbit >= GetSize(cell->getPort(portname))) {
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@ -94,15 +109,7 @@ struct AigMaker
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node.portname = portname;
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node.portbit = portbit;
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node.inverter = inverter;
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node.left_parent = -1;
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node.right_parent = -1;
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if (!aig_indices.count(node)) {
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aig_indices.expect(node, GetSize(aig->nodes));
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aig->nodes.push_back(node);
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}
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return aig_indices.at(node);
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return node2index(node);
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}
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int not_inport(IdString portname, int portbit = 0)
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@ -110,28 +117,86 @@ struct AigMaker
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return inport(portname, portbit, true);
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}
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int and_gate(int left_parent, int right_parent, bool inverter = false)
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int not_gate(int A)
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{
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if (left_parent > right_parent)
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std::swap(left_parent, right_parent);
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AigNode node;
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node.portbit = -1;
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node.inverter = inverter;
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node.left_parent = left_parent;
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node.right_parent = right_parent;
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if (!aig_indices.count(node)) {
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aig_indices.expect(node, GetSize(aig->nodes));
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aig->nodes.push_back(node);
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}
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return aig_indices.at(node);
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AigNode node(aig_indices[A]);
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node.outports.clear();
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node.inverter = !node.inverter;
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return node2index(node);
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}
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int nand_gate(int left_parent, int right_parent)
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int and_gate(int A, int B, bool inverter = false)
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{
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return and_gate(left_parent, right_parent, true);
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if (A == B)
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return A;
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const AigNode &nA = aig_indices[A];
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const AigNode &nB = aig_indices[B];
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AigNode nB_inv(nB);
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nB_inv.inverter = !nB_inv.inverter;
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if (nA == nB_inv)
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return bool_node(inverter);
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bool nA_bool = nA.portbit < 0 && nA.left_parent < 0 && nA.right_parent < 0;
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bool nB_bool = nB.portbit < 0 && nB.left_parent < 0 && nB.right_parent < 0;
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if (nA_bool && nB_bool) {
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bool bA = nA.inverter;
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bool bB = nB.inverter;
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return bool_node(inverter != (bA && bB));
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}
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if (nA_bool) {
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bool bA = nA.inverter;
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if (inverter)
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return bA ? not_gate(B) : bool_node(true);
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return bA ? B : bool_node(false);
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}
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if (nB_bool) {
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bool bB = nB.inverter;
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if (inverter)
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return bB ? not_gate(A) : bool_node(true);
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return bB ? A : bool_node(false);
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}
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AigNode node;
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node.inverter = inverter;
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node.left_parent = A;
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node.right_parent = B;
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return node2index(node);
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}
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int nand_gate(int A, int B)
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{
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return and_gate(A, B, true);
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}
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int or_gate(int A, int B)
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{
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return nand_gate(not_gate(A), not_gate(B));
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}
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int nor_gate(int A, int B)
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{
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return and_gate(not_gate(A), not_gate(B));
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}
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int xor_gate(int A, int B)
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{
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return nor_gate(and_gate(A, B), nor_gate(A, B));
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}
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int xnor_gate(int A, int B)
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{
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return or_gate(and_gate(A, B), nor_gate(A, B));
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}
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int mux_gate(int A, int B, int S)
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{
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return or_gate(and_gate(A, not_gate(S)), and_gate(B, S));
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}
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void outport(int node, IdString portname, int portbit = 0)
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@ -153,78 +218,62 @@ Aig::Aig(Cell *cell)
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for (auto p : cell->parameters)
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name += stringf(":%d", p.second.as_int());
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if (cell->type.in("$and", "$_AND_", "$_NAND_"))
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if (cell->type.in("$not", "$_NOT_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int Y = mk.not_gate(A);
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mk.outport(Y, "\\Y", i);
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}
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goto optimize;
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}
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if (cell->type.in("$and", "$_AND_", "$_NAND_", "$or", "$_OR_", "$_NOR_", "$xor", "$xnor", "$_XOR_", "$_XNOR_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int Y = mk.and_gate(A, B, cell->type == "$_NAND_");
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int Y = cell->type.in("$and", "$_AND_") ? mk.and_gate(A, B) :
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cell->type.in("$_NAND_") ? mk.nand_gate(A, B) :
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cell->type.in("$or", "$_OR_") ? mk.or_gate(A, B) :
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cell->type.in("$_NOR_") ? mk.nor_gate(A, B) :
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cell->type.in("$xor", "$_XOR_") ? mk.xor_gate(A, B) :
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cell->type.in("$xnor", "$_XNOR_") ? mk.xnor_gate(A, B) : -1;
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type.in("$or", "$_OR_", "$_NOR_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.not_inport("\\A", i);
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int B = mk.not_inport("\\B", i);
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int Y = mk.and_gate(A, B, cell->type != "$_NOR_");
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mk.outport(Y, "\\Y", i);
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}
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return;
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}
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if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int NA = mk.not_inport("\\A", i);
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int NB = mk.not_inport("\\B", i);
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int NOT_AB = mk.nand_gate(A, B);
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int NOT_NAB = mk.nand_gate(NA, NB);
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int Y = mk.and_gate(NOT_AB, NOT_NAB, !cell->type.in("$xor", "$_XOR_"));
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mk.outport(Y, "\\Y", i);
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}
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return;
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goto optimize;
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}
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if (cell->type.in("$mux", "$_MUX_"))
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{
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int S = mk.inport("\\S");
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int NS = mk.not_inport("\\S");
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int B = mk.inport("\\B", i);
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int NOT_SB = mk.nand_gate(S, B);
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int NOT_NSA = mk.nand_gate(NS, A);
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int Y = mk.nand_gate(NOT_SB, NOT_NSA);
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int Y = mk.mux_gate(A, B, S);
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mk.outport(Y, "\\Y", i);
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}
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return;
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goto optimize;
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}
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if (cell->type == "$_AOI3_")
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{
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int A = mk.inport("\\A");
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int B = mk.inport("\\B");
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int NC = mk.not_inport("\\C");
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int NOT_AB = mk.nand_gate(A, B);
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int Y = mk.and_gate(NOT_AB, NC);
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int C = mk.inport("\\C");
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int Y = mk.nor_gate(mk.and_gate(A, B), C);
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mk.outport(Y, "\\Y");
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return;
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goto optimize;
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}
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if (cell->type == "$_OAI3_")
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{
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int NA = mk.not_inport("\\A");
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int NB = mk.not_inport("\\B");
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int A = mk.inport("\\A");
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int NOT_NAB = mk.nand_gate(NA, NB);
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int Y = mk.nand_gate(NOT_NAB, C);
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int Y = mk.nand_gate(mk.or_gate(A, B), C);
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mk.outport(Y, "\\Y");
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return;
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goto optimize;
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}
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if (cell->type == "$_AOI4_")
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@ -233,27 +282,52 @@ Aig::Aig(Cell *cell)
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int D = mk.inport("\\D");
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int NOT_AB = mk.nand_gate(A, B);
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int NOT_CD = mk.nand_gate(C, D);
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int Y = mk.and_gate(NOT_AB, NOT_CD);
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int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
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mk.outport(Y, "\\Y");
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return;
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goto optimize;
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}
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if (cell->type == "$_OAI4_")
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{
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int NA = mk.not_inport("\\A");
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int NB = mk.not_inport("\\B");
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int NC = mk.not_inport("\\C");
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int ND = mk.not_inport("\\D");
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int NOT_NAB = mk.nand_gate(NA, NB);
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int NOT_NCD = mk.nand_gate(NC, ND);
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int Y = mk.nand_gate(NOT_NAB, NOT_NCD);
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int A = mk.inport("\\A");
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int D = mk.inport("\\D");
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int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D));
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mk.outport(Y, "\\Y");
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return;
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goto optimize;
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}
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name.clear();
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return;
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optimize:;
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pool<int> used_old_ids;
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vector<AigNode> new_nodes;
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dict<int, int> old_to_new_ids;
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old_to_new_ids[-1] = -1;
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for (int i = GetSize(nodes)-1; i >= 0; i--) {
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if (!nodes[i].outports.empty())
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used_old_ids.insert(i);
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if (!used_old_ids.count(i))
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continue;
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if (nodes[i].left_parent >= 0)
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used_old_ids.insert(nodes[i].left_parent);
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if (nodes[i].right_parent >= 0)
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used_old_ids.insert(nodes[i].right_parent);
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}
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for (int i = 0; i < GetSize(nodes); i++) {
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if (!used_old_ids.count(i))
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continue;
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nodes[i].left_parent = old_to_new_ids.at(nodes[i].left_parent);
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nodes[i].right_parent = old_to_new_ids.at(nodes[i].right_parent);
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old_to_new_ids[i] = GetSize(new_nodes);
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new_nodes.push_back(nodes[i]);
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}
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new_nodes.swap(nodes);
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}
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YOSYS_NAMESPACE_END
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@ -32,6 +32,7 @@ struct AigNode
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int left_parent, right_parent;
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vector<pair<IdString, int>> outports;
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AigNode();
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bool operator==(const AigNode &other) const;
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unsigned int hash() const;
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};
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@ -89,7 +89,7 @@ struct AigmapPass : public Pass {
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if (node.portbit >= 0) {
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bit = cell->getPort(node.portname)[node.portbit];
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} else if (node.left_parent < 0 && node.right_parent < 0) {
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bit = node.inverter ? State::S0 : State::S1;
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bit = node.inverter ? State::S1 : State::S0;
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goto skip_inverter;
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} else {
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SigBit A = sigs.at(node.left_parent);
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