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AigMaker refactoring

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This commit is contained in:
Clifford Wolf 2015-06-10 23:00:12 +02:00
parent e534881794
commit 1ae360cf72
4 changed files with 165 additions and 90 deletions
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2
passes/techmap/aigmap.cc
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@ -89,7 +89,7 @@ struct AigmapPass : public Pass {
if (node.portbit >= 0) {
bit = cell->getPort(node.portname)[node.portbit];
} else if (node.left_parent < 0 && node.right_parent < 0) {
bit = node.inverter ? State::S0 : State::S1;
bit = node.inverter ? State::S1 : State::S0;
goto skip_inverter;
} else {
SigBit A = sigs.at(node.left_parent);