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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/master' into xaig
This commit is contained in:
Eddie Hung
commit
1abe93e48d
15 changed files with 447 additions and 60 deletions
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@ -148,3 +148,14 @@ generate
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endgenerate
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assign out = steps[WIDTH].outer[0].val;
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endmodule
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// ------------------------------------------
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module gen_test6(output [3:0] o);
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generate
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genvar i;
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for (i = 3; i >= 0; i = i-1) begin
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assign o[i] = 1'b0;
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end
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endgenerate
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endmodule
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@ -13,7 +13,7 @@ read_verilog -formal <<EOT
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EOT
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## Examle usage for "pmuxtree" and "muxcover"
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## Example usage for "pmuxtree" and "muxcover"
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proc
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pmuxtree
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@ -49,3 +49,142 @@ hierarchy -top equiv
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equiv_simple -undef
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equiv_status -assert
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## Partial matching MUX4
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[1] == 1'b0)
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o <= i[2*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150
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select -assert-count 0 t:$_MUX_
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select -assert-count 1 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX4_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## Partial matching MUX8
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150 -mux8=200
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## Partial matching MUX16
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[3] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[3] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[8*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150 -mux8=200 -mux16=250
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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48
tests/various/shregmap.v
Normal file
48
tests/various/shregmap.v
Normal file
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@ -0,0 +1,48 @@
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module shregmap_static_test(input i, clk, output [1:0] q);
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reg head = 1'b0;
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reg [3:0] shift1 = 4'b0000;
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reg [3:0] shift2 = 4'b0000;
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always @(posedge clk) begin
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head <= i;
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shift1 <= {shift1[2:0], head};
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shift2 <= {shift2[2:0], head};
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end
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assign q = {shift2[3], shift1[3]};
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endmodule
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module $__SHREG_DFF_P_(input C, D, output Q);
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parameter DEPTH = 1;
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parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
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reg [DEPTH-1:0] r = INIT;
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always @(posedge C)
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r <= { r[DEPTH-2:0], D };
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assign Q = r[DEPTH-1];
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endmodule
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module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
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reg head = 1'b0;
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reg [3:0] shift1 = 4'b0000;
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reg [3:0] shift2 = 4'b0000;
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always @(posedge clk) begin
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head <= i;
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shift1 <= {shift1[2:0], head};
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shift2 <= {shift2[2:0], head};
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end
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assign q = {shift2[l2], shift1[l1]};
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endmodule
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module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
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parameter CLKPOL = 1;
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parameter ENPOL = 1;
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parameter DEPTH = 1;
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parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
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reg [DEPTH-1:0] r = INIT;
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wire clk = C ^ CLKPOL;
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always @(posedge C)
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r <= { r[DEPTH-2:0], D };
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assign Q = r[L];
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endmodule
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66
tests/various/shregmap.ys
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66
tests/various/shregmap.ys
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@ -0,0 +1,66 @@
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read_verilog shregmap.v
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design -save read
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design -copy-to model $__SHREG_DFF_P_
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hierarchy -top shregmap_static_test
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prep
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design -save gold
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techmap
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shregmap -init
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opt
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stat
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# show -width
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 2 t:$__SHREG_DFF_P_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 5 miter
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design -load gold
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stat
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design -load gate
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stat
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##########
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design -load read
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design -copy-to model $__XILINX_SHREG_
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hierarchy -top shregmap_variable_test
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prep
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design -save gold
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simplemap t:$dff t:$dffe
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shregmap -tech xilinx
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stat
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# show -width
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write_verilog -noexpr -norename
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 2 t:$__XILINX_SHREG_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 5 miter
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design -load gold
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stat
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design -load gate
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stat
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33
tests/various/signext.ys
Normal file
33
tests/various/signext.ys
Normal file
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@ -0,0 +1,33 @@
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read_verilog -formal <<EOT
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module gate(input clk, output [32:0] o, p, q, r, s, t, u);
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assign o = 'bx;
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assign p = 1'bx;
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assign q = 'bz;
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assign r = 1'bz;
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assign s = 1'b0;
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assign t = 'b1;
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assign u = -'sb1;
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endmodule
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EOT
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proc
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## Equivalence checking
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read_verilog -formal <<EOT
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module gold(input clk, output [32:0] o, p, q, r, s, t, u);
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assign o = {33{1'bx}};
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assign p = {{32{1'b0}}, 1'bx};
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assign q = {33{1'bz}};
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assign r = {{32{1'b0}}, 1'bz};
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assign s = {33{1'b0}};
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assign t = {{32{1'b0}}, 1'b1};
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assign u = {33{1'b1}};
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endmodule
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EOT
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proc
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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