mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 06:43:41 +00:00
Code Activity

Skip modules with memories and processes

Browse source
This commit is contained in:
Alain Dargelas 2025-02-20 11:28:50 -08:00
parent 767b498603
commit 1abb8192df
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/silimate/obs_clean.cc
View file

@ -208,6 +208,10 @@ struct ObsClean : public ScriptPass {
log("Running obs_clean pass\n"); log("Running obs_clean pass\n");
log_flush(); log_flush();
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
if (module->has_memories_warn())
continue;
SigMap sigmap(module); SigMap sigmap(module);
// Precompute cell output sigspec to cell map // Precompute cell output sigspec to cell map
dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanin; dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanin;