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Support PRIM_BUFIF1 primitive

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This commit is contained in:
Miodrag Milanovic 2021-10-14 13:04:32 +02:00
parent a0f5ba8501
commit 1aa6896966
1 changed files with 2 additions and 2 deletions
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4
frontends/verific/verific.cc
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@ -371,7 +371,7 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == PRIM_TRI) { if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput())); module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
return true; return true;
} }
@ -497,7 +497,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == PRIM_TRI) { if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput())); cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst); import_attributes(cell->attributes, inst);
return true; return true;