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rtlil: fix masquerade

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This commit is contained in:
Emil J. Tywoniak 2026-06-06 13:32:57 +02:00
parent 2d3b7e9c92
commit 1a8a95b472
11 changed files with 77 additions and 39 deletions
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2
passes/cmds/box_derive.cc
View file

@ -94,7 +94,7 @@ struct BoxDerivePass : Pass {
if (base_override)
base = base_override;
auto index = std::make_pair(base->name, cell->parameters);
auto index = std::make_pair(RTLIL::IdString(base->name), cell->parameters);
if (cell->parameters.empty())
continue;

15
passes/cmds/design.cc
View file

@ -268,11 +268,8 @@ struct DesignPass : public Pass {
{
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
RTLIL::Module *t = mod->clone();
t->name = prefix;
t->design = copy_to_design;
RTLIL::Module *t = mod->clone(copy_to_design, RTLIL::IdString(prefix));
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
done[mod->name] = prefix;
@ -300,11 +297,8 @@ struct DesignPass : public Pass {
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
RTLIL::Module *t = fmod->clone();
t->name = trg_name;
t->design = copy_to_design;
RTLIL::Module *t = fmod->clone(copy_to_design, RTLIL::IdString(trg_name));
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
done[cell->type] = trg_name;
@ -327,10 +321,7 @@ struct DesignPass : public Pass {
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
RTLIL::Module *t = mod->clone();
t->name = trg_name;
t->design = copy_to_design;
copy_to_design->add(t);
mod->clone(copy_to_design, RTLIL::IdString(trg_name));
}
}

4
passes/cmds/select.cc
View file

@ -239,12 +239,12 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
for (auto cell : mod->cells()) {
if (lhs.selected_member(mod->name, cell->name))
objects.push_back(make_pair(mod->name, cell->name));
objects.push_back(make_pair(RTLIL::IdString(mod->name), cell->name));
}
for (auto wire : mod->wires()) {
if (lhs.selected_member(mod->name, wire->name))
objects.push_back(make_pair(mod->name, wire->name));
objects.push_back(make_pair(RTLIL::IdString(mod->name), wire->name));
}
}