mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-18 13:15:46 +00:00
Code Activity

rtlil: fix masquerade

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-06 13:32:57 +02:00
parent 2d3b7e9c92
commit 1a8a95b472
11 changed files with 77 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/box_derive.cc
View file

@ -94,7 +94,7 @@ struct BoxDerivePass : Pass {
if (base_override)
base = base_override;
auto index = std::make_pair(base->name, cell->parameters);
auto index = std::make_pair(RTLIL::IdString(base->name), cell->parameters);
if (cell->parameters.empty())
continue;

15
passes/cmds/design.cc
View file

@ -268,11 +268,8 @@ struct DesignPass : public Pass {
{
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
RTLIL::Module *t = mod->clone();
t->name = prefix;
t->design = copy_to_design;
RTLIL::Module *t = mod->clone(copy_to_design, RTLIL::IdString(prefix));
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
done[mod->name] = prefix;
@ -300,11 +297,8 @@ struct DesignPass : public Pass {
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
RTLIL::Module *t = fmod->clone();
t->name = trg_name;
t->design = copy_to_design;
RTLIL::Module *t = fmod->clone(copy_to_design, RTLIL::IdString(trg_name));
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
done[cell->type] = trg_name;
@ -327,10 +321,7 @@ struct DesignPass : public Pass {
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
RTLIL::Module *t = mod->clone();
t->name = trg_name;
t->design = copy_to_design;
copy_to_design->add(t);
mod->clone(copy_to_design, RTLIL::IdString(trg_name));
}
}

4
passes/cmds/select.cc
View file

@ -239,12 +239,12 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
for (auto cell : mod->cells()) {
if (lhs.selected_member(mod->name, cell->name))
objects.push_back(make_pair(mod->name, cell->name));
objects.push_back(make_pair(RTLIL::IdString(mod->name), cell->name));
}
for (auto wire : mod->wires()) {
if (lhs.selected_member(mod->name, wire->name))
objects.push_back(make_pair(mod->name, wire->name));
objects.push_back(make_pair(RTLIL::IdString(mod->name), wire->name));
}
}

2
passes/techmap/abc9_ops.cc
View file

@ -45,7 +45,7 @@ void check(RTLIL::Design *design, bool dff_mode)
if (it == m->attributes.end())
continue;
auto id = it->second.as_int();
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), RTLIL::IdString(m->name)));
if (!r.second)
log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
m, id, r.first->second.unescape());

16
passes/techmap/clkbufmap.cc
View file

@ -145,16 +145,16 @@ struct ClkbufmapPass : public Pass {
auto wire = module->wire(port);
if (wire->get_bool_attribute(ID::clkbuf_driver))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
if (wire->get_bool_attribute(ID::clkbuf_sink))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
for (int i = 0; i < GetSize(wire); i++) {
inv_ports_out[make_pair(module->name, make_pair(wire->name, i))] = make_pair(in_name, i);
inv_ports_in[make_pair(module->name, make_pair(in_name, i))] = make_pair(wire->name, i);
inv_ports_out[make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))] = make_pair(in_name, i);
inv_ports_in[make_pair(RTLIL::IdString(module->name), make_pair(in_name, i))] = make_pair(wire->name, i);
}
}
}
@ -236,7 +236,7 @@ struct ClkbufmapPass : public Pass {
// some buffer higher up in the hierarchy.
if (wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
continue;
}
@ -249,7 +249,7 @@ struct ClkbufmapPass : public Pass {
if (buf_wire_bits.count(mapped_wire_bit)) {
// Already buffered downstream. If this is an output, mark it.
if (wire->port_output)
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
} else if (!sink_wire_bits.count(mapped_wire_bit)) {
// Nothing to do.
} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
@ -288,7 +288,7 @@ struct ClkbufmapPass : public Pass {
// A clock input in a submodule -- mark it, let higher level
// worry about it.
if (wire->port_input)
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
}
}
if (!input_bits.empty()) {
@ -320,7 +320,7 @@ struct ClkbufmapPass : public Pass {
SigBit wire_bit(wire, i);
SigBit mapped_wire_bit = sigmap(wire_bit);
if (buffered_bits.count(mapped_wire_bit))
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
}
}

10
passes/techmap/iopadmap.cc
View file

@ -217,7 +217,7 @@ struct IopadmapPass : public Pass {
// Collect explicitly-marked already-buffered SigBits.
for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(module->name, wire->name)))
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(RTLIL::IdString(module->name), wire->name)))
for (int i = 0; i < GetSize(wire); i++)
buf_bits.insert(sigmap(SigBit(wire, i)));
@ -233,7 +233,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input || wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
if (buf_bits.count(sigmap(SigBit(wire, i)))) {
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
log("Marking already mapped port: %s.%s[%d].\n", module, wire, i);
}
}
@ -293,7 +293,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
Cell *tbuf_cell = nullptr;
if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i))))
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))))
continue;
if (tbuf_bits.count(wire_bit))
@ -370,7 +370,7 @@ struct IopadmapPass : public Pass {
if (!toutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
}
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i)));
}
}
}
@ -384,7 +384,7 @@ struct IopadmapPass : public Pass {
pool<int> skip_bit_indices;
for (int i = 0; i < GetSize(wire); i++)
if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i))))
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(wire->name, i))))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))