mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
cxxrtl: expose scope information in the C++ API.
This commit adds a `debug_scopes` container, which can collect metadata about scopes in a design. Currently the only scope is that of a module. A module scope can be represented either by a module and cell pair, or a `$scopeinfo` cell in a flattened netlist. The metadata produced by the C++ API is identical between these two cases, so flattening remains transparent to a netlist with CXXRTL. The existing `debug_items` method is deprecated. This isn't strictly necessary, but the user experience is better if the path is provided as e.g. `"top "` (as some VCD viewers make it awkward to select topmost anonymous scope), and the upgrade flow encourages that, which should reduce frustration later. While the new `debug_items` method could still be broken in the future as the C++ API permits, this seems unlikely since the debug information can now capture all common netlist aspects and includes several extension points (via `debug_item`, `debug_scope` types). Also, naming of scope paths was normalized to `path` or `top_path`, as applicable.
This commit is contained in:
Catherine
parent
d903f47d41
commit
1a44645aef
5 changed files with 247 additions and 162 deletions
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@ -25,6 +25,7 @@
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#include "kernel/mem.h"
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#include "kernel/log.h"
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#include "kernel/fmt.h"
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#include "kernel/scopeinfo.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -2311,11 +2312,14 @@ struct CxxrtlWorker {
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dict<RTLIL::IdString, RTLIL::Const> attributes = object->attributes;
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// Inherently necessary to get access to the object, so a waste of space to emit.
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attributes.erase(ID::hdlname);
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// Internal Yosys attribute that should be removed but isn't.
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attributes.erase(ID::module_not_derived);
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dump_metadata_map(attributes);
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}
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void dump_debug_info_method(RTLIL::Module *module)
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{
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size_t count_scopes = 0;
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size_t count_public_wires = 0;
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size_t count_member_wires = 0;
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size_t count_undriven = 0;
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@ -2328,153 +2332,188 @@ struct CxxrtlWorker {
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size_t count_skipped_wires = 0;
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inc_indent();
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f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
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for (auto wire : module->wires()) {
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const auto &debug_wire_type = debug_wire_types[wire];
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if (!wire->name.isPublic())
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continue;
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count_public_wires++;
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switch (debug_wire_type.type) {
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case WireType::BUFFERED:
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case WireType::MEMBER: {
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// Member wire
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std::vector<std::string> flags;
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if (wire->port_input && wire->port_output)
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flags.push_back("INOUT");
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else if (wire->port_output)
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flags.push_back("OUTPUT");
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else if (wire->port_input)
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flags.push_back("INPUT");
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bool has_driven_sync = false;
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bool has_driven_comb = false;
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bool has_undriven = false;
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto bit : SigSpec(wire))
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if (!bit_has_state.count(bit))
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has_undriven = true;
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else if (bit_has_state[bit])
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has_driven_sync = true;
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else
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has_driven_comb = true;
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} else if (wire->port_output) {
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switch (cxxrtl_port_type(module, wire->name)) {
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case CxxrtlPortType::SYNC:
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has_driven_sync = true;
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break;
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case CxxrtlPortType::COMB:
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has_driven_comb = true;
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break;
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case CxxrtlPortType::UNKNOWN:
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has_driven_sync = has_driven_comb = true;
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break;
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}
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} else {
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has_undriven = true;
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}
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if (has_undriven)
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flags.push_back("UNDRIVEN");
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if (!has_driven_sync && !has_driven_comb && has_undriven)
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count_undriven++;
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if (has_driven_sync)
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flags.push_back("DRIVEN_SYNC");
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if (has_driven_sync && !has_driven_comb && !has_undriven)
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count_driven_sync++;
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if (has_driven_comb)
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flags.push_back("DRIVEN_COMB");
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if (!has_driven_sync && has_driven_comb && !has_undriven)
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count_driven_comb++;
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if (has_driven_sync + has_driven_comb + has_undriven > 1)
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count_mixed_driver++;
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset;
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bool first = true;
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for (auto flag : flags) {
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if (first) {
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first = false;
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f << ", ";
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} else {
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f << "|";
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}
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f << "debug_item::" << flag;
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}
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f << "), ";
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dump_debug_attrs(wire);
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f << indent << "if (scopes) {\n";
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inc_indent();
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// The module is responsible for adding its own scope.
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f << indent << "scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), ";
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f << escape_cxx_string(get_hdl_name(module)) << ", ";
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dump_debug_attrs(module);
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f << ", std::move(cell_attrs));\n";
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count_scopes++;
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// If there were any submodules that were flattened, the module is also responsible for adding them.
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for (auto cell : module->cells()) {
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if (cell->type != ID($scopeinfo)) continue;
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if (cell->getParam(ID::TYPE).decode_string() == "module") {
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auto module_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Module);
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auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
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cell_attrs.erase(ID::module_not_derived);
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f << indent << "scopes->add(path + " << escape_cxx_string(get_hdl_name(cell)) << ", ";
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f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", ";
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dump_metadata_map(module_attrs);
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f << ", ";
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dump_metadata_map(cell_attrs);
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f << ");\n";
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count_member_wires++;
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break;
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}
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case WireType::ALIAS: {
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// Alias of a member wire
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const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(";
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// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
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// tooling has no way to find out about the outline.
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if (debug_wire_types[aliasee].is_outline())
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f << "debug_eval_outline";
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else
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f << "debug_alias()";
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f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(aliasee);
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f << ");\n";
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count_alias_wires++;
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break;
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}
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case WireType::CONST: {
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// Wire tied to a constant
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f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
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dump_const(debug_wire_type.sig_subst.as_const());
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f << ";\n";
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(wire);
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f << ");\n";
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count_const_wires++;
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break;
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}
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case WireType::OUTLINE: {
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// Localized or inlined, but rematerializable wire
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(wire);
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f << ");\n";
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count_inline_wires++;
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break;
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}
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default: {
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// Localized or inlined wire with no debug information
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count_skipped_wires++;
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break;
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}
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} else log_assert(false && "Unknown $scopeinfo type");
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count_scopes++;
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}
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}
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto &mem : mod_memories[module]) {
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if (!mem.memid.isPublic())
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dec_indent();
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f << indent << "}\n";
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f << indent << "if (items) {\n";
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inc_indent();
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for (auto wire : module->wires()) {
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const auto &debug_wire_type = debug_wire_types[wire];
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if (!wire->name.isPublic())
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continue;
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f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
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f << ", debug_item(" << mangle(&mem) << ", ";
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f << mem.start_offset << "), ";
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if (mem.packed) {
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dump_debug_attrs(mem.cell);
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} else {
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dump_debug_attrs(mem.mem);
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count_public_wires++;
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switch (debug_wire_type.type) {
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case WireType::BUFFERED:
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case WireType::MEMBER: {
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// Member wire
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std::vector<std::string> flags;
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if (wire->port_input && wire->port_output)
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flags.push_back("INOUT");
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else if (wire->port_output)
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flags.push_back("OUTPUT");
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else if (wire->port_input)
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flags.push_back("INPUT");
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bool has_driven_sync = false;
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bool has_driven_comb = false;
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bool has_undriven = false;
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto bit : SigSpec(wire))
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if (!bit_has_state.count(bit))
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has_undriven = true;
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else if (bit_has_state[bit])
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has_driven_sync = true;
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else
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has_driven_comb = true;
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} else if (wire->port_output) {
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switch (cxxrtl_port_type(module, wire->name)) {
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case CxxrtlPortType::SYNC:
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has_driven_sync = true;
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break;
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case CxxrtlPortType::COMB:
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has_driven_comb = true;
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break;
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case CxxrtlPortType::UNKNOWN:
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has_driven_sync = has_driven_comb = true;
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break;
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}
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} else {
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has_undriven = true;
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}
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if (has_undriven)
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flags.push_back("UNDRIVEN");
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if (!has_driven_sync && !has_driven_comb && has_undriven)
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count_undriven++;
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if (has_driven_sync)
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flags.push_back("DRIVEN_SYNC");
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if (has_driven_sync && !has_driven_comb && !has_undriven)
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count_driven_sync++;
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if (has_driven_comb)
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flags.push_back("DRIVEN_COMB");
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if (!has_driven_sync && has_driven_comb && !has_undriven)
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count_driven_comb++;
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if (has_driven_sync + has_driven_comb + has_undriven > 1)
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count_mixed_driver++;
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f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset;
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bool first = true;
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for (auto flag : flags) {
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if (first) {
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first = false;
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f << ", ";
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} else {
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f << "|";
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}
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f << "debug_item::" << flag;
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}
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f << "), ";
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dump_debug_attrs(wire);
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f << ");\n";
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count_member_wires++;
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break;
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}
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case WireType::ALIAS: {
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// Alias of a member wire
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const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
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f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(";
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// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
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// tooling has no way to find out about the outline.
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if (debug_wire_types[aliasee].is_outline())
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f << "debug_eval_outline";
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else
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f << "debug_alias()";
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f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(aliasee);
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f << ");\n";
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count_alias_wires++;
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break;
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}
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case WireType::CONST: {
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// Wire tied to a constant
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f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
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dump_const(debug_wire_type.sig_subst.as_const());
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f << ";\n";
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f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(wire);
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f << ");\n";
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count_const_wires++;
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break;
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}
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case WireType::OUTLINE: {
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// Localized or inlined, but rematerializable wire
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f << indent << "items->add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), ";
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dump_debug_attrs(wire);
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f << ");\n";
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count_inline_wires++;
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break;
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}
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default: {
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// Localized or inlined wire with no debug information
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count_skipped_wires++;
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break;
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}
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}
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f << ");\n";
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}
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto &mem : mod_memories[module]) {
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if (!mem.memid.isPublic())
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continue;
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f << indent << "items->add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
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f << ", debug_item(" << mangle(&mem) << ", ";
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f << mem.start_offset << "), ";
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if (mem.packed) {
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dump_debug_attrs(mem.cell);
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} else {
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dump_debug_attrs(mem.mem);
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}
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f << ");\n";
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}
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}
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dec_indent();
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f << indent << "}\n";
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
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f << indent << mangle(cell) << access << "debug_info(items, ";
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f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
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f << indent << mangle(cell) << access;
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f << "debug_info(items, scopes, path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ", ";
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dump_debug_attrs(cell);
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f << ");\n";
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}
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}
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dec_indent();
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log_debug("Debug information statistics for module `%s':\n", log_id(module));
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log_debug(" Scopes: %zu", count_scopes);
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log_debug(" Public wires: %zu, of which:\n", count_public_wires);
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log_debug(" Member wires: %zu, of which:\n", count_member_wires);
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log_debug(" Undriven: %zu (incl. inputs)\n", count_undriven);
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@ -2522,7 +2561,8 @@ struct CxxrtlWorker {
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f << indent << "}\n";
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if (debug_info) {
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f << "\n";
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f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
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f << indent << "void debug_info(debug_items *items, debug_scopes *scopes, "
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<< "std::string path, metadata_map &&cell_attrs = {}) override {\n";
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dump_debug_info_method(module);
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f << indent << "}\n";
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}
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@ -2631,7 +2671,8 @@ struct CxxrtlWorker {
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}
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}
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f << "\n";
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f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
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f << indent << "void debug_info(debug_items *items, debug_scopes *scopes, "
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<< "std::string path, metadata_map &&cell_attrs = {}) override;\n";
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}
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dec_indent();
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f << indent << "}; // struct " << mangle(module) << "\n";
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@ -2659,7 +2700,8 @@ struct CxxrtlWorker {
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}
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f << "\n";
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f << indent << "CXXRTL_EXTREMELY_COLD\n";
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f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
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f << indent << "void " << mangle(module) << "::debug_info(debug_items *items, debug_scopes *scopes, "
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<< "std::string path, metadata_map &&cell_attrs) {\n";
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dump_debug_info_method(module);
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f << indent << "}\n";
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}
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