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Merge pull request #712 from mmicko/anlogic-support

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Initial support for Anlogic FPGA
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Clifford Wolf 2018-12-05 09:08:04 -08:00 • committed by GitHub
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8
techlibs/anlogic/Makefile.inc Normal file
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OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))

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techlibs/anlogic/anlogic_eqn.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct AnlogicEqnPass : public Pass {
AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { }
void help() YS_OVERRIDE
{
log("\n");
log(" anlogic_eqn [selection]\n");
log("\n");
log("Calculate equations for luts since bitstream generator depends on it.\n");
log("\n");
}
Const init2eqn(Const init, int inputs)
{
std::string init_bits = init.as_string();
const char* names[] = { "A" , "B", "C", "D", "E", "F" };
std::string eqn;
int width = (int)pow(2,inputs);
for(int i=0;i<width;i++)
{
if (init_bits[width-1-i]=='1')
{
eqn += "(";
for(int j=0;j<inputs;j++)
{
if (i & (1<<j))
eqn += names[j];
else
eqn += std::string("~") + names[j];
if (j!=(inputs-1)) eqn += "*";
}
eqn += ")+";
}
}
if (eqn.empty()) return Const("0");
eqn = eqn.substr(0, eqn.length()-1);
return Const(eqn);
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n");
extra_args(args, args.size(), design);
size_t cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
{
if (cell->type == "\\AL_MAP_LUT1")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT2")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT3")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT4")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT5")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT6")
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6));
cnt++;
}
}
}
log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
}
} AnlogicEqnPass;
PRIVATE_NAMESPACE_END

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techlibs/anlogic/arith_map.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
wire dummy;
(* keep *)
AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY"))
adder_cin (
.a(C[0]),
.o({COx[0], dummy})
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *)
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.c(C[Y_WIDTH]),
.o(COx[Y_WIDTH])
);
assign CO = COx[Y_WIDTH];
end
else
begin
(* keep *)
AL_MAP_ADDER #(
.ALUTYPE("ADD")
) adder_i (
.a(AA[i]),
.b(BB[i]),
.c(C[i+1]),
.o({COx[i+1],Y[i]})
);
end
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule

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module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
AL_MAP_LUT1 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]));
end else
if (WIDTH == 2) begin
AL_MAP_LUT2 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]));
end else
if (WIDTH == 3) begin
AL_MAP_LUT3 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]));
end else
if (WIDTH == 4) begin
AL_MAP_LUT4 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]));
end else
if (WIDTH == 5) begin
AL_MAP_LUT5 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]));
end else
if (WIDTH == 6) begin
AL_MAP_LUT6 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]), .f(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

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module AL_MAP_SEQ (
output q,
input ce,
input clk,
input sr,
input d
);
parameter DFFMODE = "FF"; //FF,LATCH
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
endmodule
module AL_MAP_LUT1 (
output o,
input a
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign Y = INIT >> A;
endmodule
module AL_MAP_LUT2 (
output o,
input a,
input b
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
assign o = INIT >> {b, a};
endmodule
module AL_MAP_LUT3 (
output o,
input a,
input b,
input c
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
assign o = INIT >> {c, b, a};
endmodule
module AL_MAP_LUT4 (
output o,
input a,
input b,
input c,
input d
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
assign o = INIT >> {d, c, b, a};
endmodule
module AL_MAP_LUT5 (
output o,
input a,
input b,
input c,
input d,
input e
);
parameter [31:0] INIT = 32'h0;
parameter EQN = "(A)";
assign o = INIT >> {e, d, c, b, a};
endmodule
module AL_MAP_LUT6 (
output o,
input a,
input b,
input c,
input d,
input e,
input f
);
parameter [63:0] INIT = 64'h0;
parameter EQN = "(A)";
assign o = INIT >> {f, e, d, c, b, a};
endmodule
module AL_MAP_ALU2B (
input cin,
input a0, b0, c0, d0,
input a1, b1, c1, d1,
output s0, s1, cout
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter FUNC0 = "NO";
parameter FUNC1 = "NO";
endmodule
module AL_MAP_ADDER (
input a,
input b,
input c,
output [1:0] o
);
parameter ALUTYPE = "ADD";
endmodule

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// Anlogic Eagle - Blackbox cells
// FIXME: Create sim models
(* blackbox *)
module EG_PHY_BRAM(
output [8:0] doa,
output [8:0] dob,
input [8:0] dia,
input [8:0] dib,
input [2:0] csa,
input [2:0] csb,
input cea,
input ocea,
input clka,
input wea,
input rsta,
input ceb,
input oceb,
input clkb,
input web,
input rstb,
input [12:0] addra,
input [12:0] addrb
);
parameter MODE = "DP8K";
parameter DATA_WIDTH_A = "9";
parameter DATA_WIDTH_B = "9";
parameter READBACK = "OFF";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
parameter WRITEMODE_A = "NORMAL";
parameter WRITEMODE_B = "NORMAL";
parameter GSR = "ENABLE";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CEAMUX = "SIG";
parameter CEBMUX = "SIG";
parameter OCEAMUX = "SIG";
parameter OCEBMUX = "SIG";
parameter RSTAMUX = "SIG";
parameter RSTBMUX = "SIG";
parameter CLKAMUX = "SIG";
parameter CLKBMUX = "SIG";
parameter WEAMUX = "SIG";
parameter WEBMUX = "SIG";
parameter CSA0 = "SIG" ;
parameter CSA1 = "SIG" ;
parameter CSA2 = "SIG" ;
parameter CSB0 = "SIG" ;
parameter CSB1 = "SIG" ;
parameter CSB2 = "SIG" ;
parameter INIT_FILE = "NONE";
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule
(* blackbox *)
module EG_PHY_BRAM32K(
output [15:0] doa,
output [15:0] dob,
input [15:0] dia,
input [15:0] dib,
input [10:0] addra,
input [10:0] addrb,
input bytea,
input bytewea,
input byteb,
input byteweb,
input csa,
input wea,
input csb,
input web,
input clka,
input rsta,
input clkb,
input rstb,
input ocea,
input oceb
);
parameter MODE = "DP16K";
parameter DATA_WIDTH_A = "16";
parameter DATA_WIDTH_B = "16";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
parameter WRITEMODE_A = "NORMAL";
parameter WRITEMODE_B = "NORMAL";
parameter SRMODE = "SYNC";
parameter CSAMUX = "SIG";
parameter CSBMUX = "SIG";
parameter OCEAMUX = "SIG";
parameter OCEBMUX = "SIG";
parameter RSTAMUX = "SIG";
parameter RSTBMUX = "SIG";
parameter CLKAMUX = "SIG";
parameter CLKBMUX = "SIG";
parameter WEAMUX = "SIG";
parameter WEBMUX = "SIG";
parameter READBACK = "OFF";
parameter INIT_FILE = "";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule
(* blackbox *)
module EG_PHY_FIFO(
input [8:0] dia,
input [8:0] dib,
input [2:0] csr,
input [2:0] csw,
input we,
input re,
input clkw,
input clkr,
input rst,
input rprst,
input orea,
input oreb,
output [8:0] dob,
output [8:0] doa,
output empty_flag,
output aempty_flag,
output afull_flag,
output full_flag
);
parameter MODE = "FIFO8K";
parameter DATA_WIDTH_A = "18";
parameter DATA_WIDTH_B = "18";
parameter READBACK = "OFF";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
parameter [13:0] AE = 14'b00000001100000;
parameter [13:0] AF = 14'b01111110010000;
parameter [13:0] F = 14'b01111111110000;
parameter [13:0] AEP1 = 14'b00000001110000;
parameter [13:0] AFM1 = 14'b01111110000000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [4:0] E = 5'b00000;
parameter [5:0] EP1 = 6'b010000;
parameter GSR = "ENABLE";
parameter RESETMODE = "ASYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CEA = "SIG";
parameter CEB = "SIG";
parameter OCEA = "SIG";
parameter OCEB = "SIG";
parameter RSTA = "SIG";
parameter RSTB = "SIG";
parameter CLKA = "SIG";
parameter CLKB = "SIG";
parameter WEA = "SIG";
parameter WEB = "SIG";
parameter CSA0 = "SIG";
parameter CSA1 = "SIG";
parameter CSA2 = "SIG";
parameter CSB0 = "SIG";
parameter CSB1 = "SIG";
parameter CSB2 = "SIG";
endmodule
(* blackbox *)
module EG_PHY_MULT18(
output [17:0] acout,
output [17:0] bcout,
output [35:0] p,
input signeda,
input signedb,
input [17:0] a,
input [17:0] b,
input [17:0] acin,
input [17:0] bcin,
input cea,
input ceb,
input cepd,
input clk,
input rstan,
input rstbn,
input rstpdn,
input sourcea,
input sourceb
);
parameter INPUTREGA = "ENABLE";
parameter INPUTREGB = "ENABLE";
parameter OUTPUTREG = "ENABLE";
parameter SRMODE = "ASYNC";
parameter MODE = "MULT18X18C";
parameter CEAMUX = "SIG";
parameter CEBMUX = "SIG";
parameter CEPDMUX = "SIG";
parameter RSTANMUX = "SIG";
parameter RSTBNMUX = "SIG";
parameter RSTPDNMUX = "SIG";
parameter CLKMUX = "SIG";
parameter SIGNEDAMUX = "SIG";
parameter SIGNEDBMUX = "SIG";
parameter SOURCEAMUX = "SIG";
parameter SOURCEBMUX = "SIG";
endmodule
(* blackbox *)
module EG_PHY_GCLK(
input clki,
output clko
);
endmodule
(* blackbox *)
module EG_PHY_IOCLK(
input clki,
input stop,
output clko
);
parameter STOPCLK = "DISABLE";
endmodule
(* blackbox *)
module EG_PHY_CLKDIV(
output clkdiv1,
output clkdivx,
input clki,
input rst,
input rls
);
parameter GSR = "DISABLE";
parameter DIV = 2;
endmodule
(* blackbox *)
module EG_PHY_CONFIG(
output jrstn,
output [1:0] jrti,
output jshift,
output jtck,
output jtdi,
output jupdate,
output [1:0] jscanen,
output jtms,
input [1:0] jtdo,
input [7:0] jtag8_ipa,
input [7:0] jtag8_ipb,
output done,
output highz,
output cclk,
input cclk_en,
input gsrn_sync_clk,
input usr_gsrn,
output dna_dout,
input dna_clk,
input dna_din,
input dna_shift_en,
input mboot_rebootn,
input [7:0] mboot_dynamic_addr
);
parameter MBOOT_AUTO_SEL = "DISABLE";
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b0;
parameter DONE_PERSISTN = "ENABLE";
parameter INIT_PERSISTN = "ENABLE";
parameter PROGRAMN_PERSISTN = "DISABLE";
parameter JTAG_PERSISTN = "DISABLE";
parameter GSRN_SYNC_SEL = "DISABLE";
parameter FREQ = "2.5";
parameter USR_GSRN_EN = "DISABLE";
endmodule
(* blackbox *)
module EG_PHY_OSC(
input osc_dis,
output osc_clk
);
parameter STDBY = "DISABLE";
endmodule
(* blackbox *)
module EG_PHY_PWRMNT(
output pwr_dwn_n,
input sel_pwr,
input pwr_mnt_pd
);
parameter MNT_LVL = 0;
endmodule
(* blackbox *)
module EG_PHY_DDR_8M_16(
input clk,
input clk_n,
input ras_n,
input cas_n,
input we_n,
input cs_n,
input [11:0] addr,
input [1:0] ba,
inout [15:0] dq,
input ldqs,
input udqs,
input ldm,
input udm,
input cke
);
endmodule
(* blackbox *)
module EG_PHY_SDRAM_2M_32(
input clk,
input ras_n,
input cas_n,
input we_n,
input [10:0] addr,
input [1:0] ba,
inout [31:0] dq,
input cs_n,
input dm0,
input dm1,
input dm2,
input dm3,
input cke
);
endmodule
(* blackbox *)
module EG_PHY_PAD(
input ipad,
output opad,
inout bpad,
input rst,
input ce,
input isclk,
input ipclk,
input osclk,
input opclk,
input ts,
input [3:0] do,
output di,
output [3:0] diq
);
parameter DEDCLK = "DISABLE";
parameter GSR = "ENABLE";
parameter SRMODE = "SYNC";
parameter TSMUX = "1";
parameter INSCLKMUX = "0";
parameter INPCLKMUX = "CLK";
parameter INCEMUX = "CE";
parameter INRSTMUX = "0";
parameter IN_REGSET = "RESET";
parameter IN_DFFMODE = "NONE";
parameter IDDRMODE = "OFF";
parameter IDDRPIPEMODE = "NONE";
parameter INDELMUX = "NODEL";
parameter INDEL = 0;
parameter OUTSCLKMUX = "0";
parameter OUTPCLKMUX = "CLK";
parameter OUTCEMUX = "CE";
parameter OUTRSTMUX = "0";
parameter DO_REGSET = "RESET";
parameter DO_DFFMODE = "NONE";
parameter ODDRMODE = "OFF";
parameter OUTDELMUX = "NODEL";
parameter OUTDEL = 0;
parameter TO_REGSET = "RESET";
parameter TO_DFFMODE = "NONE";
parameter MODE = "IN";
parameter DRIVE = "NONE";
parameter IOTYPE = "LVCMOS25";
endmodule
(* blackbox *)
module EG_PHY_MSLICE(
input [1:0] a,
input [1:0] b,
input [1:0] c,
input [1:0] d,
input [1:0] mi,
input clk,
input ce,
input sr,
input fci,
output [1:0] f,
output [1:0] fx,
output [1:0] q,
output fco,
input dpram_mode,
input [1:0] dpram_di,
input dpram_we,
input dpram_wclk,
input [3:0] dpram_waddr
);
parameter INIT_LUT0 = 16'h0000;
parameter INIT_LUT1 = 16'h0000;
parameter MODE = "LOGIC";
parameter ALUTYPE = "ADD";
parameter MSFXMUX = "OFF";
parameter GSR = "ENABLE";
parameter TESTMODE = "OFF";
parameter CEMUX = "CE";
parameter SRMUX = "SR";
parameter CLKMUX = "CLK";
parameter SRMODE = "ASYNC";
parameter DFFMODE = "FF";
parameter REG0_SD = "MI";
parameter REG1_SD = "MI";
parameter REG0_REGSET = "SET";
parameter REG1_REGSET = "SET";
endmodule
(* blackbox *)
module EG_PHY_LSLICE(
input [1:0] a,
input [1:0] b,
input [1:0] c,
input [1:0] d,
input [1:0] e,
input [1:0] mi,
input clk,
input ce,
input sr,
input fci,
output [1:0] f,
output [1:0] fx,
output [1:0] q,
output fco,
output [3:0] dpram_di,
output [3:0] dpram_waddr,
output dpram_wclk,
output dpram_we,
output dpram_mode
);
parameter INIT_LUTF0 = 16'h0000;
parameter INIT_LUTG0 = 16'h0000;
parameter INIT_LUTF1 = 16'h0000;
parameter INIT_LUTG1 = 16'h0000;
parameter MODE = "LOGIC";
parameter GSR = "ENABLE";
parameter TESTMODE = "OFF";
parameter CEMUX = "1";
parameter SRMUX = "SR";
parameter CLKMUX = "CLK";
parameter SRMODE = "ASYNC";
parameter DFFMODE = "FF";
parameter REG0_SD = "MI";
parameter REG1_SD = "MI";
parameter REG0_REGSET = "SET";
parameter REG1_REGSET = "SET";
parameter DEMUX0 = "D";
parameter DEMUX1 = "D";
parameter CMIMUX0 = "C";
parameter CMIMUX1 = "C";
parameter LSFMUX0 = "LUTF";
parameter LSFXMUX0 = "LUTG";
parameter LSFMUX1 = "LUTF";
parameter LSFXMUX1 = "LUTG";
endmodule
(* blackbox *)
module EG_PHY_PLL(
output [4:0] clkc,
output extlock,
input stdby,
input refclk,
input fbclk,
input reset,
output psdone,
input psclk,
input psdown,
input psstep,
input [2:0] psclksel,
output [7:0] do,
input dclk,
input dcs,
input dwe,
input [7:0] di,
input [5:0] daddr
);
parameter DYNCFG = "DISABLE";
parameter IF_ESCLKSTSW = "DISABLE";
parameter REFCLK_SEL = "INTERNAL";
parameter FIN = "100.0000";
parameter REFCLK_DIV = 1;
parameter FBCLK_DIV = 1;
parameter CLKC0_DIV = 1;
parameter CLKC1_DIV = 1;
parameter CLKC2_DIV = 1;
parameter CLKC3_DIV = 1;
parameter CLKC4_DIV = 1;
parameter CLKC0_ENABLE = "DISABLE";
parameter CLKC1_ENABLE = "DISABLE";
parameter CLKC2_ENABLE = "DISABLE";
parameter CLKC3_ENABLE = "DISABLE";
parameter CLKC4_ENABLE = "DISABLE";
parameter CLKC0_DIV2_ENABLE = "DISABLE";
parameter CLKC1_DIV2_ENABLE = "DISABLE";
parameter CLKC2_DIV2_ENABLE = "DISABLE";
parameter CLKC3_DIV2_ENABLE = "DISABLE";
parameter CLKC4_DIV2_ENABLE = "DISABLE";
parameter FEEDBK_MODE = "NORMAL";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter STDBY_ENABLE = "ENABLE";
parameter CLKC0_FPHASE = 0;
parameter CLKC1_FPHASE = 0;
parameter CLKC2_FPHASE = 0;
parameter CLKC3_FPHASE = 0;
parameter CLKC4_FPHASE = 0;
parameter CLKC0_CPHASE = 1;
parameter CLKC1_CPHASE = 1;
parameter CLKC2_CPHASE = 1;
parameter CLKC3_CPHASE = 1;
parameter CLKC4_CPHASE = 1;
parameter GMC_GAIN = 7;
parameter GMC_TEST = 14;
parameter ICP_CURRENT = 14;
parameter KVCO = 7;
parameter LPF_CAPACITOR = 3;
parameter LPF_RESISTOR = 1;
parameter PLLRST_ENA = "ENABLE";
parameter PLLMRST_ENA = "DISABLE";
parameter PLLC2RST_ENA = "DISABLE";
parameter PLLC34RST_ENA = "DISABLE";
parameter PREDIV_MUXC0 = "VCO";
parameter PREDIV_MUXC1 = "VCO";
parameter PREDIV_MUXC2 = "VCO";
parameter PREDIV_MUXC3 = "VCO";
parameter PREDIV_MUXC4 = "VCO";
parameter ODIV_MUXC0 = "DIV";
parameter ODIV_MUXC1 = "DIV";
parameter ODIV_MUXC2 = "DIV";
parameter ODIV_MUXC3 = "DIV";
parameter ODIV_MUXC4 = "DIV";
parameter FREQ_LOCK_ACCURACY = 2;
parameter PLL_LOCK_MODE = 0;
parameter INTFB_WAKE = "DISABLE";
parameter DPHASE_SOURCE = "DISABLE";
parameter VCO_NORESET = "DISABLE";
parameter STDBY_VCO_ENA = "DISABLE";
parameter NORESET = "DISABLE";
parameter SYNC_ENABLE = "ENABLE";
parameter DERIVE_PLL_CLOCKS = "DISABLE";
parameter GEN_BASIC_CLOCK = "DISABLE";
endmodule
(* blackbox *)
module EG_PHY_ADC(
input clk,
input pd,
input [2:0] s,
input soc,
output eoc,
output [11:0] dout
);
parameter CH0 = "DISABLE";
parameter CH1 = "DISABLE";
parameter CH2 = "DISABLE";
parameter CH3 = "DISABLE";
parameter CH4 = "DISABLE";
parameter CH5 = "DISABLE";
parameter CH6 = "DISABLE";
parameter CH7 = "DISABLE";
parameter VREF = "DISABLE";
endmodule

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techlibs/anlogic/synth_anlogic.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthAnlogicPass : public ScriptPass
{
SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_anlogic [options]\n");
log("\n");
log("This command runs synthesis for Anlogic FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
log(" -edif <file>\n");
log(" write the design to the specified EDIF file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, edif_file, json_file;
bool flatten, retime;
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
edif_file = "";
json_file = "";
flatten = true;
retime = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
edif_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
log_header(design, "Executing SYNTH_ANLOGIC pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() YS_OVERRIDE
{
if (check_label("begin"))
{
run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("flatten");
run("tribuf -logic");
run("deminout");
}
if (check_label("coarse"))
{
run("synth -run coarse");
}
if (check_label("fine"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
}
if (check_label("map_ffs"))
{
run("dffsr2dff");
run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
}
if (check_label("map_luts"))
{
run("abc -lut 6");
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/anlogic/cells_map.v");
run("clean");
run("anlogic_eqn");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat");
run("check -noinit");
}
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
}
}
} SynthAnlogicPass;
PRIVATE_NAMESPACE_END