mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-26 04:56:05 +00:00
intel_alm: Add multiply signedness to cells
Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
This commit is contained in:
parent
4f2b78e19a
commit
1a07b330f8
7 changed files with 147 additions and 16 deletions
|
@ -565,7 +565,9 @@ endmodule
|
|||
module cyclonev_mac(ax, ay, resulta);
|
||||
|
||||
parameter ax_width = 9;
|
||||
parameter signed_max = "true";
|
||||
parameter ay_scan_in_width = 9;
|
||||
parameter signed_may = "true";
|
||||
parameter result_a_width = 18;
|
||||
parameter operation_mode = "M9x9";
|
||||
|
||||
|
@ -579,7 +581,9 @@ endmodule
|
|||
module cyclone10gx_mac(ax, ay, resulta);
|
||||
|
||||
parameter ax_width = 18;
|
||||
parameter signed_max = "true";
|
||||
parameter ay_scan_in_width = 18;
|
||||
parameter signed_may = "true";
|
||||
parameter result_a_width = 36;
|
||||
parameter operation_mode = "M18X18_FULL";
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue