Merge commit

tests/opt/opt_dff_qd.ys

@@ -7,7 +7,7 @@ module top(...);
 input CLK;
 input EN;
 (* init = 24'h555555 *)
-output [19:0] Q;
+output [17:0] Q;
 input SRST;
 input ARST;
 input [1:0] CLR;
@@ -23,26 +23,20 @@ $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_V
 $dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(Q[15:14]), .Q(Q[15:14]));
 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(Q[17:16]), .Q(Q[17:16]));
 
-$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff9 (.EN(EN), .D(Q[19:18]), .Q(Q[19:18]));
-$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff10 (.EN(EN), .ARST(ARST), .D(Q[21:20]), .Q(Q[21:20]));
-$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff11 (.EN(EN), .SET(SET), .CLR(CLR), .D(Q[23:22]), .Q(Q[23:22]));
-
 endmodule
 
 EOT
 
 design -save orig
 
-# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
-delete top/ff10 top/ff11
 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 
 design -load orig
 opt_dff -keepdc
 select -assert-count 1 t:$and
 select -assert-count 3 t:$dffe
-select -assert-count 3 t:$dlatch
-select -assert-count 3 t:$sr
+select -assert-count 2 t:$dlatch
+select -assert-count 2 t:$sr
 select -assert-none t:$and t:$dffe t:$dlatch t:$sr %% %n t:* %i
 
 design -load orig
@@ -50,7 +44,7 @@ simplemap
 opt_dff -keepdc
 select -assert-count 2 t:$_AND_
 select -assert-count 6 t:$_DFFE_??_
-select -assert-count 6 t:$_DLATCH_?_
-select -assert-count 6 t:$_SR_??_
+select -assert-count 4 t:$_DLATCH_?_
+select -assert-count 4 t:$_SR_??_
 select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
 

tests/various/check.ys

@@ -0,0 +1,43 @@
+design -reset
+read -vlog2k <<EOF
+module top(input clk, input a, input b, output [9:0] x);
+	wire [9:0] ripple;
+	reg [9:0] prev_ripple = 9'b0;
+
+	always @(posedge clk) prev_ripple <= ripple;
+	assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
+	assign x = ripple[9] + b;
+endmodule
+EOF
+hierarchy -top top
+prep
+check -assert
+
+design -reset
+read -vlog2k <<EOF
+module top(clk, y, sideread_addr, sideread_data);
+	input wire clk;
+
+	reg [7:0] mem [255:0];
+	reg [8:0] i;
+	initial begin
+		for (i = 0; i < 256; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	output reg [7:0] y = 1;
+	always @(posedge clk)
+		y <= mem[y];
+
+	input wire [7:0] sideread_addr;
+	output wire [7:0] sideread_data;
+	assign sideread_data = mem[sideread_addr];
+endmodule
+EOF
+hierarchy -top top
+prep -rdff
+select -assert-count 1 t:$mem_v2
+check -assert
+memory_unpack
+select -assert-count 2 t:$memrd_v2
+check -assert

tests/various/check_2.ys

@@ -0,0 +1,17 @@
+# just so slightly adjust the example from check.ys to induce a loop
+design -reset
+read -vlog2k <<EOF
+module top(input clk, input a, input b, output [9:0] x);
+	wire [9:0] ripple;
+	reg [9:0] prev_ripple = 9'b0;
+
+	always @(posedge clk) prev_ripple <= ripple;
+	assign ripple = {ripple[8:1], a, ripple[0]} ^ prev_ripple;
+	assign x = ripple[9] + b;
+endmodule
+EOF
+hierarchy -top top
+prep
+logger -expect warning "found logic loop in module top:" 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+check -assert

tests/various/check_3.ys

@@ -0,0 +1,20 @@
+# loop involving asynchronous memory ports
+design -reset
+read -vlog2k <<EOF
+module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
+	reg [3:0] mem [15:0];
+	reg [5:0] i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	assign y1 = mem[{y2[3:2], x}];
+	assign y2 = mem[y1];
+endmodule
+EOF
+hierarchy -top pingpong
+prep
+logger -nowarn "found logic loop in module pingpong:"
+logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
+check -assert

tests/various/check_4.ys

@@ -0,0 +1,29 @@
+# loop involving the asynchronous reset on a memory port
+design -reset
+read -vlog2k <<EOF
+module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
+	reg [3:0] mem [15:0];
+	reg [5:0] i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	wire arst = !data[0];
+
+	always @(posedge arst, posedge clk) begin
+		if (arst)		
+			data <= 4'hx;
+		else
+			data <= mem[addr];
+	end
+endmodule
+EOF
+hierarchy -top top
+proc
+opt -keepdc
+memory_dff
+opt_clean
+logger -nowarn "found logic loop in module pingpong:"
+logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
+check -assert