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akash 2024-03-29 19:30:48 -07:00
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docs/source/using_yosys/synthesis/proc.rst
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@ -31,7 +31,7 @@ Example
|code_examples/synth_flow|_.
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
.. literalinclude:: /code_examples/synth_flow/proc_01.v
:language: verilog