Merge commit

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -18,7 +18,7 @@ in the circuit diagrams generated by it. The code used is included in the Yosys
 code base under |code_examples/show|_.
 
 .. |code_examples/show| replace:: :file:`docs/source/code_examples/show`
-.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/show
+.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show
 
 A simple circuit
 ^^^^^^^^^^^^^^^^
@@ -337,7 +337,7 @@ The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
 
 .. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler`
-.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/scrambler
+.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler
 
 Changing design hierarchy
 ^^^^^^^^^^^^^^^^^^^^^^^^^

docs/source/using_yosys/more_scripting/model_checking.rst

@@ -29,7 +29,7 @@ Let's take a look at an example included in the Yosys code base under
 |code_examples/synth_flow|_:
 
 .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
-.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
 
 .. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
    :language: verilog
@@ -81,7 +81,7 @@ The code used in this section is included in the Yosys code base under
 |code_examples/axis|_.
 
 .. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
-.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/axis
+.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis
 
 The following AXI4 Stream Master has a bug. But the bug is not exposed if the
 slave keeps ``tready`` asserted all the time. (Something a test bench might do.)

docs/source/using_yosys/more_scripting/selections.rst

@@ -405,7 +405,7 @@ those cases selection variables must be used to capture more complex selections.
 Example code from |code_examples/selections|_:
 
 .. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections`
-.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/selections
+.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections
 
 .. literalinclude:: /code_examples/selections/select.v
    :language: verilog

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -21,7 +21,7 @@ detail in the :doc:`/getting_started/example_synth` document.
    
    To learn more about these commands, check out :ref:`interactive_show`.
 
-.. _example project: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/intro
+.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
 
 A simple counter
 ~~~~~~~~~~~~~~~~

docs/source/using_yosys/synthesis/extract.rst

@@ -15,7 +15,7 @@ The extract pass
 Example code can be found in |code_examples/macc|_.
 
 .. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc`
-.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/macc
+.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/macc
 
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.ys

docs/source/using_yosys/synthesis/memory.rst

@@ -36,7 +36,7 @@ Example
 |code_examples/synth_flow|_.
 
 .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
-.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
 
 .. figure:: /_images/code_examples/synth_flow/memory_01.*
    :class: width-helper
@@ -92,7 +92,7 @@ leftover memory cells unable to be converted are then picked up by
 
 For more on the lib format for :cmd:ref:`memory_libmap`, see
 `passes/memory/memlib.md
-<https://github.com/YosysHQ/yosys/blob/master/passes/memory/memlib.md>`_
+<https://github.com/YosysHQ/yosys/blob/main/passes/memory/memlib.md>`_
 
 Supported memory patterns
 ^^^^^^^^^^^^^^^^^^^^^^^^^

docs/source/using_yosys/synthesis/proc.rst

@@ -31,7 +31,7 @@ Example
 |code_examples/synth_flow|_.
 
 .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
-.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
 
 .. literalinclude:: /code_examples/synth_flow/proc_01.v
    :language: verilog