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Implemented part/bit select on memory read

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This commit is contained in:
Clifford Wolf 2013-11-20 10:51:32 +01:00
parent d248419fe0
commit 19dba2561e
4 changed files with 104 additions and 5 deletions
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41
tests/simple/memory.v
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@ -17,3 +17,44 @@ always @(posedge clk)
endmodule
// ----------------------------------------------------------
module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
input clk, setA, setB;
input [1:0] addr;
input [2:0] bit;
output reg y1, y2;
output y3, y4;
reg [7:0] mem1 [3:0];
(* mem2reg *)
reg [7:0] mem2 [3:0];
always @(posedge clk) begin
if (setA) begin
mem1[0] <= 10;
mem1[1] <= 20;
mem1[2] <= 30;
mem2[0] <= 17;
mem2[1] <= 27;
mem2[2] <= 37;
end
if (setB) begin
mem1[0] <= 1;
mem1[1] <= 2;
mem1[2] <= 3;
mem2[0] <= 71;
mem2[1] <= 72;
mem2[2] <= 73;
end
y1 <= mem1[addr][bit];
y2 <= mem2[addr][bit];
end
assign y3 = mem1[addr][bit];
assign y4 = mem2[addr][bit];
endmodule