From 1990c1fac54d8cbb70b64b3687085fcb4c83f8a1 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Tue, 13 May 2025 20:42:47 -0700 Subject: [PATCH] Reduce pass verbosity --- passes/opt/opt_reduce.cc | 28 ++++++++++++++-------------- passes/opt/opt_share.cc | 6 +++--- passes/opt/wreduce.cc | 22 +++++++++++----------- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 323e7b6fb..f683fa354 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -93,7 +93,7 @@ struct OptReduceWorker new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1; if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { - log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); + log_debug(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; total_count++; } @@ -156,7 +156,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::B, new_sig_b); @@ -243,7 +243,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size()) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::A, new_sig_a); @@ -309,7 +309,7 @@ struct OptReduceWorker if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0) return; - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; total_count++; @@ -389,12 +389,12 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); if (cell->type != ID($bmux)) { - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); } else { - log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); } @@ -423,15 +423,15 @@ struct OptReduceWorker cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle)); if (cell->type != ID($bmux)) { - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); } else { - log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); } } - log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); + log_debug(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); module->connect(old_sig_conn); did_something = true; @@ -480,8 +480,8 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log_debug(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); if (swizzle.empty()) { @@ -500,11 +500,11 @@ struct OptReduceWorker cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle)); - log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_debug(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); } - log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); + log_debug(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); module->connect(old_sig_conn); did_something = true; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 76afe6201..96319f181 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -558,13 +558,13 @@ struct OptSharePass : public Pass { } for (auto &shared : merged_ops) { - log(" Found cells that share an operand and can be merged by moving the %s %s in front " + log_debug(" Found cells that share an operand and can be merged by moving the %s %s in front " "of " "them:\n", log_id(shared.mux->type), log_id(shared.mux)); for (const auto& op : shared.ports) - log(" %s\n", log_id(op.op)); - log("\n"); + log_debug(" %s\n", log_id(op.op)); + log_debug("\n"); merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap); } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 6a92a5641..532aad96c 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -110,7 +110,7 @@ struct WreduceWorker return; } - log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", + log_debug("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type)); int n_removed = GetSize(sig_removed); @@ -209,7 +209,7 @@ struct WreduceWorker return; } - log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before, + log_debug("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before, log_id(module), log_id(cell), log_id(cell->type)); for (auto bit : sig_d) @@ -257,7 +257,7 @@ struct WreduceWorker } if (bits_removed) { - log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", + log_debug("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort(stringf("\\%c", port), sig); did_something = true; @@ -330,7 +330,7 @@ struct WreduceWorker } if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) { - log("Converting cell %s.%s (%s) from unsigned to signed.\n", + log_debug("Converting cell %s.%s (%s) from unsigned to signed.\n", log_id(module), log_id(cell), log_id(cell->type)); cell->setParam(ID::A_SIGNED, 1); cell->setParam(ID::B_SIGNED, 1); @@ -338,7 +338,7 @@ struct WreduceWorker port_b_signed = true; did_something = true; } else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) { - log("Converting cell %s.%s (%s) from signed to unsigned.\n", + log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n", log_id(module), log_id(cell), log_id(cell->type)); cell->setParam(ID::A_SIGNED, 0); cell->setParam(ID::B_SIGNED, 0); @@ -358,7 +358,7 @@ struct WreduceWorker SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { - log("Converting cell %s.%s (%s) from signed to unsigned.\n", + log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n", log_id(module), log_id(cell), log_id(cell->type)); cell->setParam(ID::A_SIGNED, 0); cell->setParam(ID::B_SIGNED, 0); @@ -371,7 +371,7 @@ struct WreduceWorker if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) { SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { - log("Converting cell %s.%s (%s) from signed to unsigned.\n", + log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n", log_id(module), log_id(cell), log_id(cell->type)); cell->setParam(ID::A_SIGNED, 0); port_a_signed = false; @@ -437,7 +437,7 @@ struct WreduceWorker } if (bits_removed) { - log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", + log_debug("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort(ID::Y, sig); did_something = true; @@ -510,7 +510,7 @@ struct WreduceWorker if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)]) continue; - log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); + log_debug("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); Wire *nw = module->addWire(module->uniquify(IdString(w->name.str() + "_wreduce")), GetSize(w) - unused_top_bits); module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->swap_names(w, nw); @@ -618,7 +618,7 @@ struct WreducePass : public Pass { B.remove(GetSize(B)-1, 1); } if (original_b_width != GetSize(B)) { - log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", + log_debug("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type)); c->setPort(ID::B, B); c->setParam(ID::B_WIDTH, GetSize(B)); @@ -632,7 +632,7 @@ struct WreducePass : public Pass { int cur_addrbits = c->getParam(ID::ABITS).as_int(); int max_addrbits = ceil_log2(mem->start_offset + mem->size); if (cur_addrbits > max_addrbits) { - log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", + log_debug("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", cur_addrbits-max_addrbits, cur_addrbits, c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", log_id(module), log_id(c), log_id(memid));