mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

memory: Introduce $meminit_v2 cell, with EN input.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-05-21 02:26:52 +02:00
parent 37d76deef1
commit 19720b970d
10 changed files with 86 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

24
techlibs/common/simlib.v
View file

@ -2233,6 +2233,30 @@ endmodule
// --------------------------------------------------------
module \$meminit_v2 (ADDR, DATA, EN);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter WORDS = 1;
parameter PRIORITY = 0;
input [ABITS-1:0] ADDR;
input [WORDS*WIDTH-1:0] DATA;
input [WIDTH-1:0] EN;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $meminit_v2!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";